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1. 发明申请

US20050021874A1 Single chip protocol converter 有权
标题翻译：单芯片协议转换器
公开(公告)号：US20050021874A1
公开(公告)日：2005-01-27
申请号：US10768828
申请日：2004-01-30
申请人： Christos Georgiou , Victor Gregurick , Indira Nair , Valentina Salapura
发明人： Christos Georgiou , Victor Gregurick , Indira Nair , Valentina Salapura
IPC分类号： G06F15/80 , G06F9/38 , G06F15/16 , G06F15/76 , G06F15/78
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

2. 发明申请

US20050021871A1 SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN 有权
标题翻译：自包含处理器子系统作为系统片上设计的组件
公开(公告)号：US20050021871A1
公开(公告)日：2005-01-27
申请号：US10604491
申请日：2003-07-25
申请人： Christos Georgiou , Victor Gregurick , Valentina Salapura
发明人： Christos Georgiou , Victor Gregurick , Valentina Salapura
IPC分类号： G06F15/80 , G06F15/16 , G06F15/78
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译：一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。

3. 发明申请

US20070239966A1 SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN 有权
标题翻译：自包含处理器子系统作为系统片上设计的组件
公开(公告)号：US20070239966A1
公开(公告)日：2007-10-11
申请号：US11757166
申请日：2007-06-01
申请人： Christos Georgiou , Victor Gregurick , Valentina Salapura
发明人： Christos Georgiou , Victor Gregurick , Valentina Salapura
IPC分类号： G06F15/76
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译：一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。

4. 发明申请

US20050008011A1 METHOD AND SYSTEM OF DATA TRANSFER FOR EFFICIENT MEMORY UTILIZATION 失效
标题翻译：数据传输的方法和系统有效的记忆利用
公开(公告)号：US20050008011A1
公开(公告)日：2005-01-13
申请号：US10604295
申请日：2003-07-09
申请人： Christos Georgiou , Valentina Salapura
发明人： Christos Georgiou , Valentina Salapura
IPC分类号： H04L12/56
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9052
摘要： A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.
摘要翻译：提供了一种方法和系统来有效地管理接收可变大小的分组的网络设备中的存储器。存储器被分配到部分，由此包括多个相等大小的缓冲器的每个部分接收特定大小的分组。一部分用于较小的分组大小，另一部分用于较大的分组大小，但可以创建其他部分。当在网络设备处接收到分组时，它们基于它们的大小被存储到适当的存储器部分中。监视每个部分中的可用缓冲器的数量，使得当其低于阈值时，缓冲器被重新分配到另一个，从而增加总体存储器效率。

5. 发明申请

US20050025152A1 METHOD AND SYSTEM OF EFFICIENT PACKET REORDERING 失效
标题翻译：高效包装的方法与系统
公开(公告)号：US20050025152A1
公开(公告)日：2005-02-03
申请号：US10604557
申请日：2003-07-30
申请人： Christos Georgiou , Valentina Salapura
发明人： Christos Georgiou , Valentina Salapura
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

6. 发明申请

US20050246434A1 Services for capturing and modeling computer usage 审中-公开
标题翻译：用于捕获和建模计算机使用的服务
公开(公告)号：US20050246434A1
公开(公告)日：2005-11-03
申请号：US10818159
申请日：2004-04-05
申请人： David Bantz , Peter Capek , Thomas Chefalas , David Chess , Christos Georgiou , William Grey , Steven Mastrianni , Paul Moskowitz , Clifford Pickover
发明人： David Bantz , Peter Capek , Thomas Chefalas , David Chess , Christos Georgiou , William Grey , Steven Mastrianni , Paul Moskowitz , Clifford Pickover
IPC分类号： G06F7/60 , G06F15/173 , G06F17/10 , H04Q3/00
CPC分类号： H04Q3/0029
摘要： A subscriber to a service that monitors user behavior first registers with that service and selects a model of user behavior. The service then transmits that model to an agent, situated capable of monitoring user behavior and relating it to the model. After the monitoring interval the agent transmits data from the model to a server, where that data is summarized and reports created. These reports can then be sent to the subscriber in satisfaction of their needs for behavioral information.
摘要翻译：监视用户行为的服务的订户首先向该服务注册并选择用户行为模型。然后，该服务将该模型发送到能够监视用户行为并将其与模型相关联的代理。在监视间隔之后，代理程序将数据从模型发送到服务器，在那里对数据进行汇总和创建报告。然后可以将这些报告发送给用户以满足他们对行为信息的需求。

7. 发明申请

US20080037568A1 Method and Apparatus for Translating Data Packets From One Network Protocol to Another 审中-公开
标题翻译：将数据包从一个网络协议翻译成另一个的方法和装置
公开(公告)号：US20080037568A1
公开(公告)日：2008-02-14
申请号：US11840478
申请日：2007-08-17
申请人： Richard Anderson , Marc Faucher , Christos Georgiou , Francis Noel
发明人： Richard Anderson , Marc Faucher , Christos Georgiou , Francis Noel
IPC分类号： H04L12/56
CPC分类号： H04L69/22 , H04L69/08
摘要： A method for translating data packets from one network protocol to another is disclosed. A set of translation templates is constructed. The translation templates are then loaded into a translation template cache. In response to a data packet from a first network arriving at a translation router, an appropriate translation template is selected from the set of translation templates within the translation template cache according to the translation context of the data packet. Next, a new header for transmission into a second network is constructed by reading header fields of the data packet from the first network along with the appropriate translation template in the translation template cache. The data payload of the data packet from the first network is subsequently removed from the header of the data packet and then appended to the constructed header of the second network. Finally, the newly constructed data packet is transmitted to the second network.
摘要翻译：公开了一种将数据分组从一个网络协议转换到另一个网络协议的方法。构建了一套翻译模板。然后将翻译模板加载到翻译模板缓存中。响应于来自第一网络的到达转换路由器的数据分组，根据数据分组的转换上下文，从翻译模板高速缓存中的一组翻译模板中选择适当的翻译模板。接下来，通过从翻译模板高速缓存中读取来自第一网络的数据分组的头部字段以及适当的翻译模板来构建用于传输到第二网络的新标题。来自第一网络的数据分组的数据有效载荷随后从数据分组的报头中移除，然后附加到构建的第二网络的报头。最后，新建的数据包被传送到第二个网络。

8. 发明申请

US20060235957A1 CONNECTION MANAGEMENT METHOD, SYSTEM, AND PROGRAM PRODUCT 审中-公开
标题翻译：连接管理方法，系统和程序产品
公开(公告)号：US20060235957A1
公开(公告)日：2006-10-19
申请号：US11379611
申请日：2006-04-21
申请人： Marc Faucher , Christos Georgiou , Ann Rincon
发明人： Marc Faucher , Christos Georgiou , Ann Rincon
IPC分类号： G06F15/173
CPC分类号： H04L67/2819 , H04L43/0811 , H04L43/16 , H04L67/2842
摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.
摘要翻译：本发明提供了一种用于管理连接的方法，系统和程序产品。特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

9. 发明申请

US20050091364A1 Method and system for on-demand allocation of a dynamic network of services 失效
标题翻译：动态服务网络按需分配的方法和系统
公开(公告)号：US20050091364A1
公开(公告)日：2005-04-28
申请号：US10674962
申请日：2003-09-30
申请人： David Bantz , David Chess , Christos Georgiou , Jeffrey Kephart , Clifford Pickover
发明人： David Bantz , David Chess , Christos Georgiou , Jeffrey Kephart , Clifford Pickover
IPC分类号： G06Q50/00 , G06F15/173 , G06Q30/00 , H04L12/00 , H04L12/56 , H04L29/08 , H04M3/00
CPC分类号： H04L67/1008 , H04L67/1002 , H04L67/1029
摘要： A system and method for providing real-time, dynamic switching between first and second service providers each capable of providing a service for users over a communications network. The method includes steps of: establishing switching criterion for deciding when to switch service provision between the first service provider and second service provider; maintaining state information associated with a user's use of the service provided by a first service provider; switching between the first and second service provided over the communications network based on satisfaction of the switching criterion; and, migrating any state information maintained up to the time of switching to the second service. Preferably, the dynamic switching occurs in a manner substantially transparent to the user.
摘要翻译：一种用于在第一和第二服务提供商之间提供实时动态切换的系统和方法，每个服务提供商能够通过通信网络为用户提供服务。该方法包括以下步骤：建立用于决定何时切换第一服务提供商和第二服务提供商之间的服务提供的切换标准; 维护与用户对由第一服务提供商提供的服务的使用相关联的状态信息; 基于切换标准的满足，在通信网络上提供的第一和第二服务之间切换; 并且将维护的任何状态信息迁移到切换到第二服务的时间。优选地，动态切换以对用户基本透明的方式发生。

10. 发明申请

US20060168283A1 Programmable network protocol handler architecture 失效
标题翻译：可编程网络协议处理器架构
公开(公告)号：US20060168283A1
公开(公告)日：2006-07-27
申请号：US11387875
申请日：2006-03-24
申请人： Christos Georgiou , Monty Denneau
发明人： Christos Georgiou , Monty Denneau
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F9/5027 , G06F2209/5018 , H04L47/125
摘要： An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via a high-speed interconnect, using a multi-token counter protocol for data transmission between processors and between processors and memory. Each processor's memory is globally accessible by other processors, and memory synchronization operations are used to obviate the need for “spin-locks”. Each processor has multiple threads, each capable of fully executing programs. Each processor contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing. The high-speed protocol handler may also provide built-in monitors for examining the activity of its hardware resources and reallocating the workload to the resources that are not heavily used, thus balancing the resource utilization and increasing the workload throughput.
摘要翻译：在网络协议处理器中实现高速性能的架构将多个可编程处理器中的并行性和流水线结合在一起，以及处理时间关键协议操作的网络接口处的专用前端逻辑。多处理器通过高速互连互连，使用多令牌计数器协议在处理器之间以及处理器和存储器之间进行数据传输。每个处理器的存储器可由其他处理器全局访问，并且使用存储器同步操作来消除对“自旋锁”的需要。每个处理器有多个线程，每个线程都能完全执行程序。每个处理器都包含嵌入式动态随机存取存储器（DRAM）。处理器中的线程以并行/流水线方式分配各种协议功能的处理。数据帧处理由一个或多个线程完成以识别相关帧。相关帧被调度到相同的线程，以便最小化与存储器访问和通用协议处理相关联的开销。高速协议处理器还可以提供用于检查其硬件资源的活动并将工作负载重新分配给未被大量使用的资源的内置监视器，从而平衡资源利用并增加工作负载的吞吐量。

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