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1. 发明申请

US20050273545A1 Flexible techniques for associating cache memories with processors and main memory 失效
公开(公告)号：US20050273545A1
公开(公告)日：2005-12-08
申请号：US11197899
申请日：2005-08-05
申请人： Monty Denneau , Peter Hochschild , Henry Warren
发明人： Monty Denneau , Peter Hochschild , Henry Warren
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F2212/601
摘要： Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.

2. 发明申请

US20050254492A1 Methods for routing packets on a linear array of processors 失效
标题翻译：在线性阵列处理器上路由数据包的方法
公开(公告)号：US20050254492A1
公开(公告)日：2005-11-17
申请号：US11186693
申请日：2005-07-21
申请人： Monty Denneau , Peter Hochschild , Richard Swetz , Henry Warren
发明人： Monty Denneau , Peter Hochschild , Richard Swetz , Henry Warren
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： G06F15/17381 , G06F15/17337
摘要： There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.
摘要翻译：提供了一种用于在以最近邻配置连接的N个处理器的线性阵列上路由分组的方法。该方法包括对于阵列的每个终端处理器将未使用的输出连接到相应的未使用的输入的步骤。对于将数据包从源直接路由到目标处理器所需的每个轴，执行以下步骤。确定是否将分组从初始处理器直接发送到目标处理器的结果分别小于或大于N / 2移动。初始处理器是第一个轴中的源处理器，目标处理器是最后一个轴上的目标处理器。当结果小于N / 2移动时，数据包从初始处理器直接发送到目标处理器。当结果大于N / 2移动时，数据包被间接发送以便包围每个终端处理器。该方法可以可选地包括当结果等于N / 2移动并且N是偶数时，使用任一发送步骤随机发送分组的步骤。

3. 发明申请

US20060168283A1 Programmable network protocol handler architecture 失效
标题翻译：可编程网络协议处理器架构
公开(公告)号：US20060168283A1
公开(公告)日：2006-07-27
申请号：US11387875
申请日：2006-03-24
申请人： Christos Georgiou , Monty Denneau
发明人： Christos Georgiou , Monty Denneau
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F9/5027 , G06F2209/5018 , H04L47/125
摘要： An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via a high-speed interconnect, using a multi-token counter protocol for data transmission between processors and between processors and memory. Each processor's memory is globally accessible by other processors, and memory synchronization operations are used to obviate the need for “spin-locks”. Each processor has multiple threads, each capable of fully executing programs. Each processor contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing. The high-speed protocol handler may also provide built-in monitors for examining the activity of its hardware resources and reallocating the workload to the resources that are not heavily used, thus balancing the resource utilization and increasing the workload throughput.
摘要翻译：在网络协议处理器中实现高速性能的架构将多个可编程处理器中的并行性和流水线结合在一起，以及处理时间关键协议操作的网络接口处的专用前端逻辑。多处理器通过高速互连互连，使用多令牌计数器协议在处理器之间以及处理器和存储器之间进行数据传输。每个处理器的存储器可由其他处理器全局访问，并且使用存储器同步操作来消除对“自旋锁”的需要。每个处理器有多个线程，每个线程都能完全执行程序。每个处理器都包含嵌入式动态随机存取存储器（DRAM）。处理器中的线程以并行/流水线方式分配各种协议功能的处理。数据帧处理由一个或多个线程完成以识别相关帧。相关帧被调度到相同的线程，以便最小化与存储器访问和通用协议处理相关联的开销。高速协议处理器还可以提供用于检查其硬件资源的活动并将工作负载重新分配给未被大量使用的资源的内置监视器，从而平衡资源利用并增加工作负载的吞吐量。

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