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1. 发明申请

US20120267719A1 Method and Apparatus for use in Improving Linearity of MOSFETS using an Accumulated Charge Sink-Harmonic Wrinkle Reduction 有权
标题翻译：用于改善MOSFETs线性度的方法和装置，使用累积电荷沉降式抗皱消除
公开(公告)号：US20120267719A1
公开(公告)日：2012-10-25
申请号：US13277108
申请日：2011-10-19
申请人： Christopher N. Brindle , Jie Deng , Alper Genc , Chieh-Kai Yang
发明人： Christopher N. Brindle , Jie Deng , Alper Genc , Chieh-Kai Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/7841 , H01L29/0688 , H01L29/36 , H01L29/78609 , H01L29/78615 , H01L29/78681 , H01L29/78684 , H03K2217/0018 , H03K2217/0054
摘要： A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
摘要翻译：公开了一种用于提高具有累积电荷吸收（ACS）的MOSFET器件的线性灵敏度的方法和装置。该方法和装置适于解决在采用累积电荷宿的装置中在期望工作电压范围内的二阶和三阶互调谐波失真的劣化。

2. 发明授权

US08742502B2 Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction 有权
标题翻译：用于提高使用累积电荷沉降谐波皱纹减少的MOSFET的线性度的方法和装置
公开(公告)号：US08742502B2
公开(公告)日：2014-06-03
申请号：US13277108
申请日：2011-10-19
申请人： Christopher N. Brindle , Jie Deng , Alper Genc , Chieh-Kai Yang
发明人： Christopher N. Brindle , Jie Deng , Alper Genc , Chieh-Kai Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/7841 , H01L29/0688 , H01L29/36 , H01L29/78609 , H01L29/78615 , H01L29/78681 , H01L29/78684 , H03K2217/0018 , H03K2217/0054
摘要： A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
摘要翻译：公开了一种用于提高具有累积电荷吸收（ACS）的MOSFET器件的线性灵敏度的方法和装置。该方法和装置适于解决在采用累积电荷宿的装置中在期望的工作电压范围内的二阶和三阶互调谐波失真的劣化。

3. 发明授权

US08686140B2 Method of purifying a salt, sodium salt and disodium salt of pemetrexed 有权
标题翻译：培美曲塞的盐，钠盐和二钠盐的纯化方法
公开(公告)号：US08686140B2
公开(公告)日：2014-04-01
申请号：US12739576
申请日：2008-10-21
申请人： Jie Luo , Meng Lin , Bo Lin , Wenrun Ye , Yongmei Qin , Jie Deng
发明人： Jie Luo , Meng Lin , Bo Lin , Wenrun Ye , Yongmei Qin , Jie Deng
IPC分类号： C07D487/04
CPC分类号： C07D487/04
摘要： A method of purifying a salt of pemetrexed having a structure of formula (III) by salting-out, wherein if M3+ is H+, then each of M1+ and M2+ is independently H+, Li+, Na+ or K+, provided that both of them are not H+; if M3+ is Li+, Na+ or K+, then each of M1+ and M2+ is independently Li+, Na+ or K+.
摘要翻译：通过盐析纯化具有式（III）结构的培美曲塞盐的方法，其中如果M3 +为H +，则M1 +和M2 +各自独立地为H +，Li +，Na +或K +，条件是它们都不是 H +; 如果M3 +为Li +，Na +或K +，则M1 +和M2 +各自独立为Li +，Na +或K +。

4. 发明授权

US08563721B2 Morphinan derivatives and preparation methods thereof 失效
标题翻译：吗啡喃衍生物及其制备方法
公开(公告)号：US08563721B2
公开(公告)日：2013-10-22
申请号：US13000200
申请日：2009-06-19
申请人： Huafu Sun , Jie Luo , Wenrun Ye , Jie Deng , Bo Lin , Chunyan Dan , Bin Fan
发明人： Huafu Sun , Jie Luo , Wenrun Ye , Jie Deng , Bo Lin , Chunyan Dan , Bin Fan
IPC分类号： C07F7/02 , C07D489/08
CPC分类号： C07D489/08 , C07D489/09
摘要： The present invention relates to morphinan derivatives and preparation methods thereof, especially to ketal hydroxyl protected compounds of morphinan derivatives and preparation method thereof, and to a method for preparing corresponding alkylated morphinan derivatives by using the ketal hydroxyl protected compounds as intermediates, and more especially to a ketal hydroxyl protected compound of methylnaltrexone as intermediate for preparing methylnaltrexone and a method for preparing methylnaltrexone through said intermediate.
摘要翻译：本发明涉及吗啡喃衍生物及其制备方法，尤其涉及缩酮羟基保护的吗啡喃衍生物化合物及其制备方法，以及通过使用缩酮羟基保护的化合物作为中间体制备相应的烷基化吗啡喃衍生物的方法，更具体地涉及作为制备甲基纳曲酮的中间体的甲基纳曲酮的缩酮羟基保护的化合物和通过所述中间体制备甲基纳曲酮的方法。

5. 发明申请

US20120214877A1 STABLE RASAGILINE COMPOSITION 有权
标题翻译：稳定的RASAGILINE组合物
公开(公告)号：US20120214877A1
公开(公告)日：2012-08-23
申请号：US13504178
申请日：2010-10-28
申请人： Jialiang Lin , Jie Deng , Hao Chen , Tao Zhang
发明人： Jialiang Lin , Jie Deng , Hao Chen , Tao Zhang
IPC分类号： A61K31/135 , A61P25/14 , A61P25/28 , A61P25/16
CPC分类号： A61K31/135 , A61K9/0014 , A61K9/06 , A61K9/7061 , A61K9/7069 , A61K31/355 , A61K31/375 , A61K47/10 , A61K47/22 , A61K2300/00
摘要： The present invention provides a stable composition of rasagiline comprising an effective dosage of rasagiline or its pharmaceutically acceptable salts and an antioxidant used as a stabilizer. The dosage forms of the composition are pharmaceutically common transdermal-drug delivery dosage form and mucoadhesive delivery dosage form, such as patch, gel, ointment, cream, cataplasm, film, spray and solution, etc. The composition can be used to prevent or treat mental disorders.
摘要翻译：本发明提供雷沙吉兰的稳定组合物，其包含有效剂量的雷沙吉兰或其药学上可接受的盐和用作稳定剂的抗氧化剂。组合物的剂型是药学上常见的透皮 - 药物递送剂型和粘膜粘附递送剂型，例如贴剂，凝胶，软膏，霜剂，粘膜，膜，喷雾剂和溶液等。该组合物可用于预防或治疗精神错乱。

6. 发明申请

US20110082680A1 COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS 失效
标题翻译：用于器件/电路/芯片泄漏电流（IDDQ）的紧凑型模型包括工艺引起的升级因素
公开(公告)号：US20110082680A1
公开(公告)日：2011-04-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50 , G06F17/18 , G01R31/26
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

7. 发明申请

US20100306687A1 SYSTEM AND METHOD FOR AVATAR MANAGEMENT 审中-公开
标题翻译： AVATAR管理系统与方法
公开(公告)号：US20100306687A1
公开(公告)日：2010-12-02
申请号：US12856367
申请日：2010-08-13
申请人： Jie Deng
发明人： Jie Deng
IPC分类号： G06F15/16 , G06F3/048
CPC分类号： H04L67/38
摘要： The present invention provides a system for avatar management, including at least one client and a server, the client is adapted to assemble an avatar according to operation of a user, generate avatar information corresponding to the avatar, transmit the avatar information to the server via a network requesting the server to update the avatar of the user; the server is adapted to parse the avatar information to obtain the corresponding avatar, generate a snapshot based on the avatar, store and manage the avatar information and corresponding snapshot; the server further informs at least one client to update the avatar of the user; and the at least one client updates the avatar of the user according to the snapshot. The present invention also provides a method for avatar management. The present invention can save bandwidth of the server, speed snapshot generation, improve security and accuracy of snapshot generation, and increase system efficiency.
摘要翻译：本发明提供了一种用于化身管理的系统，包括至少一个客户端和服务器，该客户机适于根据用户的操作来组装化身，生成与该化身相对应的化身信息，并将该化身信息通过请求服务器更新用户的化身的网络; 服务器适于解析化身信息以获得相应的化身，基于头像生成快照，存储和管理化身信息和对应的快照; 服务器还通知至少一个客户端来更新用户的化身; 并且所述至少一个客户端根据所述快照更新所述用户的化身。本发明还提供了一种用于化身管理的方法。本发明可以节省服务器的带宽，快速生成快照，提高快照生成的安全性和准确性，提高系统效率。

8. 发明授权

US08626480B2 Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors 失效
标题翻译：紧凑型器件/电路/芯片泄漏电流（IDDQ）计算，包括工艺引起的隆起因素
公开(公告)号：US08626480B2
公开(公告)日：2014-01-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

9. 发明授权

US08237197B2 Asymmetric channel MOSFET 失效
标题翻译：非对称沟道MOSFET
公开(公告)号：US08237197B2
公开(公告)日：2012-08-07
申请号：US12831310
申请日：2010-07-07
申请人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
发明人： Xiangdong Chen , Jie Deng , Weipeng Li , Deleep R. Nair , Jae-Eun Park , Daniel Tekleab , Xiaobin Yuan , Nam Sung Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/823412 , H01L21/28202 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7833 , H01L29/7834 , H01L29/7835
摘要： A field effect transistor includes a partial SiGe channel, i.e., a channel including a SiGe channel portion, located underneath a gate electrode and a Si channel portion located underneath an edge of the gate electrode near the drain region. The SiGe channel portion can be located directly underneath a gate dielectric, or can be located underneath a Si channel layer located directly underneath a gate dielectric. The Si channel portion is located at the same depth as the SiGe channel portion, and contacts the drain region of the transistor. By providing a Si channel portion near the drain region, the GIDL current of the transistor is maintained at a level on par with the GIDL current of a transistor having a silicon channel only during an off state.
摘要翻译：场效应晶体管包括部分SiGe沟道，即包括位于栅极下方的SiGe沟道部分的沟道部分，以及位于漏极区域附近的位于栅电极的边缘下方的Si沟道部分。 SiGe沟道部分可以位于栅极电介质的正下方，或者可以位于位于栅极电介质正下方的Si沟道层下方。 Si沟道部分位于与SiGe沟道部分相同的深度处，并与晶体管的漏极区域接触。通过在漏极区附近提供Si沟道部分，晶体管的GIDL电流仅在断开状态下保持在与具有硅沟道的晶体管的GIDL电流相同的水平上。

10. 发明授权

US07590972B2 Role-oriented development environment 有权
标题翻译：以角色为导向的发展环境
公开(公告)号：US07590972B2
公开(公告)日：2009-09-15
申请号：US10975975
申请日：2004-10-28
申请人： Jeffrey Axelrod , Sameer Shalaby , Jay Gitterman , William Herndon , Jie Deng
发明人： Jeffrey Axelrod , Sameer Shalaby , Jay Gitterman , William Herndon , Jie Deng
IPC分类号： G06F9/44 , G06F17/30
CPC分类号： G06Q99/00 , Y10S707/99939
摘要： This invention relates to a business application development and execution environment that recognizes and supports various development and user roles. Aspects of the method and system are adapted to builders, assemblers, power users and end users.
摘要翻译：本发明涉及一种识别和支持各种开发和用户角色的业务应用开发和执行环境。方法和系统的方面适用于建筑商，装配商，高级用户和最终用户。

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