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1. 发明授权

US6115789A Method and system for determining which memory locations have been accessed in a self timed cache architecture 失效
标题翻译：用于确定在自定时高速缓存结构中已经访问了哪些存储器位置的方法和系统
公开(公告)号：US6115789A
公开(公告)日：2000-09-05
申请号：US845868
申请日：1997-04-28
申请人： Christopher McCall Durham , Hieu Trong Ngo , Peter Juergen Klim
发明人： Christopher McCall Durham , Hieu Trong Ngo , Peter Juergen Klim
IPC分类号： G11C29/32 , G06F12/00 , G11C29/00
CPC分类号： G11C29/32
摘要： The present invention provides a method and system for providing observability of memory address access for self-timed cache designs. A system according to the present invention for determining which memory location has been accessed in a self-timed cache comprises a content addressable memory; a secondary memory coupled to the content addressable memory, wherein the secondary memory includes at least one memory location which may be selected by the content addressable memory based upon a self-timed cache access. The system further includes a test circuitry coupled to the content addressable memory, wherein the test circuitry stores a pointer which points to a selected memory location in response to the self-timed cache access of the secondary memory.
摘要翻译：本发明提供了一种用于提供用于自定时高速缓存设计的存储器地址访问的可观察性的方法和系统。根据本发明的用于确定在自定时高速缓存中已经访问了哪个存储器位置的系统包括内容可寻址存储器; 耦合到内容可寻址存储器的辅助存储器，其中辅存储器包括可以由内容可寻址存储器基于自定时高速缓存访问来选择的至少一个存储器位置。系统还包括耦合到内容可寻址存储器的测试电路，其中测试电路响应于辅助存储器的自定时高速缓存访问而存储指向所选存储器位置的指针。

2. 发明授权

US06406980B1 Physical design technique providing single and multiple core microprocessor chips in a single design cycle and manufacturing lot using shared mask sets 失效
标题翻译：物理设计技术在单个设计周期中提供单核和多核微处理器芯片，并使用共享掩模集提供制造批次
公开(公告)号：US06406980B1
公开(公告)日：2002-06-18
申请号：US09645155
申请日：2000-08-24
申请人： Matthew J. Amatangelo , Christopher McCall Durham , Peter Juergen Klim , Stephen Larry Runyon
发明人： Matthew J. Amatangelo , Christopher McCall Durham , Peter Juergen Klim , Stephen Larry Runyon
IPC分类号： H01L21301
CPC分类号： H01L27/0207 , H01L27/118
摘要： A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.
摘要翻译：提供了使用单个用于晶片的掩模的然后在所期望的芯片类型的时候产生多个集成芯片类型的晶片设计布局和方法，使用几个定制步骤来产生最终的集成芯片。在一个实施例中，晶片布局包括多个组件分组和多个分割通道，每个分组通道将组件中的每一个与其他部件分离。在选择了期望的特定类型的集成电路芯片之后，晶片可以处理最后几个层，并且使用用于集成电路芯片的合适的切割通道去除芯片。

3. 发明授权

US5896059A Decoupling capacitor fuse system 失效
标题翻译：去耦电容保险丝系统
公开(公告)号：US5896059A
公开(公告)日：1999-04-20
申请号：US854224
申请日：1997-05-09
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K19/003 , H03K3/01
CPC分类号： H03K19/003
摘要： An apparatus to remove from operation a decoupling capacitor connected to a power supply providing power to logic circuitry in an integrated circuit. One technique for doing so is to connect a fuse in series with a decoupling capacitor. The present invention amplifies current transmitting through the fuse in a positive feedback manner to force the fuse to blow sooner than would normally occur. Therefore, when the current through the decoupling capacitor is deemed unacceptable, the fuse current is increased until such a time that the fuse opens.
摘要翻译：一种用于从操作中去除连接到向集成电路中的逻辑电路提供电力的电源的去耦电容器的装置。一种这样做的技术是将保险丝与去耦电容串联。本发明以正反馈方式放大通过保险丝传输的电流，以使熔丝比通常发生的更快地吹动。因此，当通过去耦电容器的电流被认为是不可接受的时候，熔丝电流增加直至熔丝开启的时间为止。

4. 发明授权

US06785826B1 Self power audit and control circuitry for microprocessor functional units 失效
标题翻译：用于微处理器功能单元的自检审计和控制电路
公开(公告)号：US06785826B1
公开(公告)日：2004-08-31
申请号：US08682471
申请日：1996-07-17
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A method and apparatus for reducing power dissipation within a functional unit of a microprocessor includes a power sensing circuit for sensing power dissipation of the functional unit. A low power mode identifying circuit identifies when the measured power dissipation of the functional unit exceeds a predetermined amount or value. Upon such a condition, a low power mode circuit operates the functional unit in a low power mode thereby reducing its power dissipation. Operation of the functional unit in the low power mode continues until the power dissipation reaches a safe level. The functional unit internally determines power dissipation and selectively enters a low power mode to reduce power dissipation of the functional unit. Low power mode operation of the functional unit reduces power dissipation of the functional unit.
摘要翻译：一种用于降低微处理器的功能单元内功耗的方法和装置，包括用于感测功能单元的功耗的功率检测电路。低功率模式识别电路识别功能单元的测量功耗何时超过预定量或值。在这种情况下，低功率模式电路以低功率模式操作功能单元，从而降低其功耗。低功耗模式下的功能单元的运行持续到功耗达到安全水平。功能单元内部确定功耗，并选择性地进入低功耗模式以降低功能单元的功耗。功能单元的低功耗模式操作降低了功能单元的功耗。

5. 发明授权

US06522170B1 Self-timed CMOS static logic circuit 失效
标题翻译：自定时CMOS静态逻辑电路
公开(公告)号：US06522170B1
公开(公告)日：2003-02-18
申请号：US09067153
申请日：1998-04-27
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K1900
CPC分类号： H03K19/0966
摘要： A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.
摘要翻译：已经发明了一种自定时CMOS静态电路技术，其提供了对源电路的完全握手; 通过互锁内部和外部信号来防止输入数据丢失; 电路和接收器之间完全握手自定时电路; 借助于输出数据信息的内部锁定来防止丢失的访问操作信息; 以及一些类型的动态自定时系统的插件兼容性。整个系统的最终结果是现在可以使用静态CMOS电路来生成自定时系统。这与依赖于动态电路的现有自定时系统形成对比。因此，可以保持静态电路的质量并充分利用它们。

6. 发明授权

US06285217B1 Dynamic logic circuits with reduced evaluation time 失效
标题翻译：动态逻辑电路减少评估时间
公开(公告)号：US06285217B1
公开(公告)日：2001-09-04
申请号：US09391423
申请日：1999-09-08
申请人： Christopher McCall Durham , Peter Juergen Klim , Younes Lofti , John Beck
发明人： Christopher McCall Durham , Peter Juergen Klim , Younes Lofti , John Beck
IPC分类号： H03K19096
CPC分类号： G11C7/065
摘要： Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.
摘要翻译：具有减少评估时间的动态逻辑电路通过提高逻辑输入梯级的连接点处的电压变化率，在动态评估逻辑电路方面提供更快的输出。一旦节点开始评估，这些电路使用交叉耦合放大器对输入梯形图组合节点进行充电。

7. 发明授权

US5790560A Apparatus and method for timing self-timed circuitry 失效
标题翻译：定时自定时电路的装置和方法
公开(公告)号：US5790560A
公开(公告)日：1998-08-04
申请号：US767247
申请日：1996-12-13
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： G01R31/28 , G01R31/30 , G01R31/3193
CPC分类号： G01R31/30 , G01R31/2882 , G01R31/31937
摘要： A method and apparatus for timing self-timed circuitry measures the cycle time of a self-timed system or circuit. An input pattern generator generates a plurality of data input patterns that are sequentially input to the self-timed system or circuit. A valid output signal, generated after the self-timed system or circuit produces output signal(s) in response to each data input pattern and signals the input pattern generator to change the input to the next data input pattern. A timer measures the total amount of time required for the self-timed system or circuit to generate output signal(s) in response to the sequential input of each of the data input patterns. A counter counts the number of times a valid output signal is generated as the apparatus loops through each of the data input patterns. The timer result is divided by the counter result to determine the average cycle time (time delay) of a self-timed system or circuit across multiple data input patterns.
摘要翻译：用于定时自定时电路的方法和装置测量自定时系统或电路的周期时间。输入图案生成器生成顺序地输入到自定时系统或电路的多个数据输入模式。在自定时系统或电路之后产生的有效输出信号响应于每个数据输入模式产生输出信号，并且向输入模式发生器发信号，以将输入改变为下一个数据输入模式。定时器测量自适应系统或电路响应于每个数据输入模式的顺序输入而产生输出信号所需的总时间量。当计数器循环通过每个数据输入模式时，计数器计数生成有效输出信号的次数。定时器结果除以计数器结果，以确定跨多个数据输入模式的自定时系统或电路的平均周期时间（时间延迟）。

8. 发明授权

US06269045B1 Self-timed address decoder for register file and compare circuit of multi-port cam 失效
标题翻译：多端口凸轮的寄存器文件和比较电路的自定时地址解码器
公开(公告)号：US06269045B1
公开(公告)日：2001-07-31
申请号：US09500348
申请日：2000-02-08
申请人： Christopher McCall Durham , Peter Juergen Klim , Roy Keith Waite
发明人： Christopher McCall Durham , Peter Juergen Klim , Roy Keith Waite
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.
摘要翻译：电路评估多个数据输入，提供评估的稳定性，然后驱动来自电路的评估。通过延迟控制评估电路的激活信号来执行稳定化的提供。激活信号可以是时钟信号或复位信号。该电路可以是在评估阶段解码某些地址信号的地址解码器，然后在第二阶段期间驱动评估。

9. 发明授权

US06209055B1 Method and apparatus for reducing noise induced among conductive lines 失效
标题翻译：用于降低导线间感应的噪声的方法和装置
公开(公告)号：US06209055B1
公开(公告)日：2001-03-27
申请号：US09182301
申请日：1998-10-29
申请人： Christopher McCall Durham , Peter Juergen Klim , John Andrew Beck
发明人： Christopher McCall Durham , Peter Juergen Klim , John Andrew Beck
IPC分类号： G06F1300
CPC分类号： G11C7/10 , G11C5/063 , G11C7/18
摘要： For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.
摘要翻译：为了在多个集成电路导线上发送信息，在集成电路的路径上设置n条导线。路径具有第一和第二部分，以及插入的过渡部分。这些线在第一部分中具有相对于彼此的第一位置，并且某些线改变了过渡部分中的相对位置，使得线在第二部分中具有彼此相对的第二位置。信息被编码成格式，其中n行中不超过一行具有一次在其上被声明的信号，使得在线之间引起的噪声降低。

10. 发明授权

US06181156B2 Noise suppression circuits for suppressing noises above and below reference voltages 失效
标题翻译：用于抑制高于和低于参考电压的噪声的噪声抑制电路
公开(公告)号：US06181156B2
公开(公告)日：2001-01-30
申请号：US09282269
申请日：1999-03-31
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K1716
CPC分类号： H03K17/223 , H03K3/356008 , H03K5/1252 , H03K19/00361 , H04L25/08
摘要： A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.
摘要翻译：公开了一种用于抑制高于和低于参考电压的噪声的噪声抑制电路。用于抑制噪声的噪声抑制电路包括用于产生上电复位信号的装置，钳位晶体管和反馈电路。用于产生上电复位信号的装置将噪声抑制电路的内部锁存器预设为诸如逻辑高状态的预定状态。在发生噪声耦合事件之后，钳位晶体管恢复噪声抑制电路提供保护的电路的数据输入的状态。然后，反馈电路在预定的时间量之后关断钳位晶体管。

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