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1. 发明授权

US6133759A Decoupled reset dynamic logic circuit 失效
标题翻译：去耦合复位动态逻辑电路
公开(公告)号：US6133759A
公开(公告)日：2000-10-17
申请号：US97794
申请日：1998-06-16
申请人： John Andrew Beck , Robert Paul Masleid , Thomas Robert Toms
发明人： John Andrew Beck , Robert Paul Masleid , Thomas Robert Toms
IPC分类号： H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.
摘要翻译：实现了动态逻辑电路，其将输出的复位与评估节点的复位分离。 N树逻辑电路响应于第一组输入信号产生逻辑输出信号。输出信号耦合到并联耦合的一对NFET器件的第一n型场效应晶体管（NFET）的栅极。并联漏极耦合到动态逻辑电路的输出，并联源耦合到地。该对的第二NFET器件的栅极分别耦合到串联连接的p型场效应晶体管（PFET）器件和第三NFET器件的源极和漏极的结。第三NFET器件具有耦合到地的源极，并且PFET器件具有耦合到电压源的漏极。 PFET器件和第三NFET器件的栅极连接在一起并接收逻辑信号，由此可以复位动态逻辑电路的输出。

2. 发明授权

US6055557A Adder circuit and method therefor 失效
标题翻译：加法器电路及其方法
公开(公告)号：US6055557A
公开(公告)日：2000-04-25
申请号：US780561
申请日：1997-01-08
申请人： John Andrew Beck , James Edward Dunning , John Stephen Muhich
发明人： John Andrew Beck , James Edward Dunning , John Stephen Muhich
IPC分类号： G06F7/50 , G06F7/505 , G06F7/508
CPC分类号： G06F7/505
摘要： An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.
摘要翻译：加法器（300）产生编码输出以节省功率。特别地，加法器提供“B2”编码的输出，其仅在数据处理系统中的导线上每次驱动一位每两位一个位。二进制输入由编码器（800,304）编码以产生多个位。多个比特被级联以形成多个和值。然后响应于进位停止信号，进位产生信号和进位传播信号的逻辑值选择性地输出多个和值的一部分。

3. 发明授权

US6147508A Power consumption control mechanism and method therefor 失效
标题翻译：功耗控制机制及其方法
公开(公告)号：US6147508A
公开(公告)日：2000-11-14
申请号：US137776
申请日：1998-08-20
申请人： John Andrew Beck , David William Boerstler , Christopher McCall Durham , Peter Juergen Klim
发明人： John Andrew Beck , David William Boerstler , Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K19/00 , H03K17/16 , H03K3/011 , H03K19/0948
CPC分类号： H03K19/0013 , H03K19/0027 , H03K2217/0018
摘要： An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.
摘要翻译：实现了用于控制逻辑设备的功耗的装置和方法。互补金属氧化物半导体（CMOS）逻辑器件的功耗以及因此的速度基本上与器件的速度成比例。通过调整构成控制逻辑器件的金属氧化物半导体（MOS）器件的阈值电压来控制器件速度来控制逻辑器件的温度。通过在其中制造每个被控制的器件的散装材料和器件的最正电极之间施加反向偏置电压来控制器件的阈值电压。响应于逻辑器件温度来调节背偏置电压值，从而闭合反馈回路。

4. 发明授权

US5821850A Method and apparatus for comparing magnitude of data from a plurality of data sources 失效
标题翻译：用于比较来自多个数据源的数据的幅度的方法和装置
公开(公告)号：US5821850A
公开(公告)日：1998-10-13
申请号：US710441
申请日：1996-09-17
申请人： John Andrew Beck
发明人： John Andrew Beck
IPC分类号： G06F7/02 , G05B1/00
CPC分类号： G06F7/026
摘要： An information handling system includes a data comparison circuit which includes a number of multi-bit comparison circuit modules, wherein each of the multi-bit comparison circuit modules includes a circuit for comparing two or more bits from a first data source with two or more bits from a second data source to produce an output indicating that the data bits from the first data source are equal to the data bits from the second data source; one or more AND gates for ANDing output signals from each of the first set of circuit modules to produce an output signal if all bits in the first data source are equal to all bits in a second data source; one or more second circuit modules for providing an output signal indicating that data bits from the first data source are unequal to corresponding data bits from the second data source; and one or more inequality combination circuits combining inequality signals from each of the second set of circuit modules to produce an output when value of data from the first data source is unequal to the value of data from the second data source. The unequal compare may typically produce a signal indicating that the selected data bits from the first data source are greater than the corresponding data bits from the second data source. Alternatively, the unequal compare can be used to indicate a less than compare condition.
摘要翻译：信息处理系统包括数据比较电路，其包括多个比特电路模块，其中每个多比特比较电路模块包括用于将来自第一数据源的两个或多个比特与两个或多个比特从第二数据源产生指示来自第一数据源的数据位等于来自第二数据源的数据位的输出; 一个或多个与门，用于对来自第一组电路模块中的每一个的输出信号进行“与”运算，以产生输出信号，如果第一数据源中的所有位都等于第二数据源中的所有位; 一个或多个第二电路模块，用于提供指示来自第一数据源的数据位不等于来自第二数据源的相应数据位的输出信号; 以及一个或多个不等式组合电路，其组合来自第二组电路模块的不等式信号，以在来自第一数据源的数据的值不等于来自第二数据源的数据的值时产生输出。不等比较通常可以产生指示来自第一数据源的选定数据位大于来自第二数据源的相应数据位的信号。或者，不等比较可用于指示小于比较条件。

5. 发明授权

US5784330A Evenly distributed RC delay word line decoding and mapping 失效
标题翻译：均匀分布的RC延迟字线解码和映射
公开(公告)号：US5784330A
公开(公告)日：1998-07-21
申请号：US752981
申请日：1996-12-02
申请人： John Andrew Beck , Terry Lee Leasure , Gus Wai-Yan Yeung
发明人： John Andrew Beck , Terry Lee Leasure , Gus Wai-Yan Yeung
IPC分类号： G11C8/10 , G11C8/14 , G11C8/00
CPC分类号： G11C8/14 , G11C8/10
摘要： A device for accessing a specific word line in a memory array has improved noise protection by smoothing out the RC load in the word line mapping circuit. The word lines are respectively connected to rows of memory cells in the memory array, and predecoded word lines are used to decode encoded addresses which correspond to the various rows. The circuit connects the word lines to the predecoded word lines by gates which are tapped into the predecoded word lines, and the taps on a given predecoded word line are non-adjacent, to more evenly distribute the RC delay for each predecoded word line. In other words, the word lines are interspersed, out of order. The word lines can be interspersed randomly, or according to a predetermined function, such as a modulo function. The RC load for a given predecoded word line is preferably uniformly distributed along substantially the entire length of the predecoded word line.
摘要翻译：用于访问存储器阵列中的特定字线的装置通过平滑字线映射电路中的RC负载来改善噪声保护。字线分别连接到存储器阵列中的存储器单元的行，并且预解码字线用于对与各行对应的编码地址进行解码。该电路通过被抽头到预解码字线的栅极将字线连接到预解码字线，并且给定预解码字线上的抽头不相邻，以便为每个预编码字线更均匀地分配RC延迟。换句话说，字线散布，不正常。字线可以随机散布，或者根据预定的功能，例如模函数。用于给定预解码字线的RC负载优选地基本上在预解码字线的整个长度上均匀分布。

6. 发明授权

US06209055B1 Method and apparatus for reducing noise induced among conductive lines 失效
标题翻译：用于降低导线间感应的噪声的方法和装置
公开(公告)号：US06209055B1
公开(公告)日：2001-03-27
申请号：US09182301
申请日：1998-10-29
申请人： Christopher McCall Durham , Peter Juergen Klim , John Andrew Beck
发明人： Christopher McCall Durham , Peter Juergen Klim , John Andrew Beck
IPC分类号： G06F1300
CPC分类号： G11C7/10 , G11C5/063 , G11C7/18
摘要： For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.
摘要翻译：为了在多个集成电路导线上发送信息，在集成电路的路径上设置n条导线。路径具有第一和第二部分，以及插入的过渡部分。这些线在第一部分中具有相对于彼此的第一位置，并且某些线改变了过渡部分中的相对位置，使得线在第二部分中具有彼此相对的第二位置。信息被编码成格式，其中n行中不超过一行具有一次在其上被声明的信号，使得在线之间引起的噪声降低。

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