专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140019780A1 ACTIVE POWER DISSIPATION DETECTION BASED ON ERRONOUS CLOCK GATING EQUATIONS 有权
标题翻译：基于错误时钟评估方法的主动断电检测
公开(公告)号：US20140019780A1
公开(公告)日：2014-01-16
申请号：US13550207
申请日：2012-07-16
申请人： Christopher M. Abernathy , Maarten J. Boersma , Markus Kaltenbach , Ulrike Schmidt
发明人： Christopher M. Abernathy , Maarten J. Boersma , Markus Kaltenbach , Ulrike Schmidt
IPC分类号： G06F1/24 , G06F1/00
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method detects active power dissipation in an integrated circuit. The method includes receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a clock domain, wherein the local clock buffer is configured to receive a clock signal and an actuation signal. The method includes adding instrumentation logic to the design for the clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the clock domain is in an idle condition. The method includes detecting the clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal.
摘要翻译：一种方法可以检测集成电路中的有功功率。该方法包括接收具有一个或多个时钟域的集成电路的硬件设计，其中硬件设计包括用于时钟域的本地时钟缓冲器，其中本地时钟缓冲器被配置为接收时钟信号和致动信号。该方法包括将仪器逻辑添加到时钟域的设计中，其中仪器逻辑被配置为将在测试周期的起始点确定的致动信号的第一值与每次确定的致动信号的第二值进行比较当时钟域处于空闲状态时。响应于致动信号的第一值不等于致动信号的第二值，该方法包括检测时钟域包括非预期的有功功耗。

2. 发明授权

US08631223B2 Register file supporting transactional processing 失效
标题翻译：注册文件支持事务处理
公开(公告)号：US08631223B2
公开(公告)日：2014-01-14
申请号：US12778235
申请日：2010-05-12
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3004 , G06F9/30087 , G06F9/30138 , G06F9/384
摘要： A processor includes an instruction sequencing unit, execution unit, and multi-level register file including a first level register file having a lower access latency and a second level register file having a higher access latency. Responsive to the processor processing a second instruction in a transactional code section to obtain as an execution result a second register value of the logical register, the mapper moves a first register value of the logical register to the second level register file, places the second register value in the first level register file, marks the second register value as speculative, and replaces a first mapping for the logical register with a second mapping. Responsive to unsuccessful termination of the transactional code section, the mapper designates the second register value in the first level register file as invalid so that the first register value in the second level register file becomes the working value.
摘要翻译：处理器包括指令排序单元，执行单元和多级寄存器文件，其包括具有较低访问延迟的第一级寄存器文件和具有较高访问延迟的第二级寄存器文件。响应于处理器处理事务代码部分中的第二指令以获得逻辑寄存器的第二寄存器值作为执行结果，映射器将逻辑寄存器的第一寄存器值移动到第二级寄存器堆，将第二寄存器在第一级寄存器文件中的值，将第二寄存器值标记为推测，并用第二映射替换逻辑寄存器的第一映射。响应于事务代码段的不成功终止，映射器将第一级寄存器文件中的第二寄存器值指定为无效，使得第二级寄存器文件中的第一寄存器值变为工作值。

3. 发明申请

US20120216004A1 THREAD TRANSITION MANAGEMENT 失效
标题翻译：螺纹过渡管理
公开(公告)号：US20120216004A1
公开(公告)日：2012-08-23
申请号：US13032737
申请日：2011-02-23
申请人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Susan E. Eisen , James A. Kahle , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F12/02
CPC分类号： G06F9/30101 , G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/461
摘要： Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination.
摘要翻译：可以使用各种系统，过程，产品和技术来管理线程转换。在特定实现中，用于管理线程转换的系统和过程可以包括确定要对两个数据寄存器组的相对使用进行转换的能力，并且基于转换确定来确定是否将线程数据移入至少一个数据寄存器设置为二级寄存器。系统和过程还可以包括基于移动确定将线程数据从至少一个数据寄存器集合移动到第二级寄存器的能力。

4. 发明授权

US08239661B2 System and method for double-issue instructions using a dependency matrix 失效
标题翻译：使用依赖矩阵的双重指令的系统和方法
公开(公告)号：US08239661B2
公开(公告)日：2012-08-07
申请号：US12199853
申请日：2008-08-28
申请人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , Todd A. Venton
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3838 , G06F9/3017 , G06F9/3867
摘要： A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method cancels the second portion issue.
摘要翻译：一种用于双重复杂指令的方法接收包括第一部分和第二部分的复杂指令。该方法设置单个问题队列插槽，并为复杂指令分配执行单元，并识别第一和第二部分的依赖关系。该方法为第一和部分部分设置依赖矩阵槽和消费者表槽。在满足第一部分依赖性的情况下，该方法发出第一部分，然后从单个问题队列插槽中发出第二部分。在第二部分相关性尚未得到满足的情况下，该方法取消了第二部分问题。

5. 发明申请

US20090006817A1 Mechanisms for Placing a Processor into a Gradual Slow Mode of Operation 有权
标题翻译：将处理器置于逐渐缓慢运行模式的机制
公开(公告)号：US20090006817A1
公开(公告)日：2009-01-01
申请号：US12204865
申请日：2008-09-05
申请人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, JR.
发明人： Christopher M. Abernathy , Kurt A. Feiste , Ronald P. Hall , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/524
摘要： Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed in accordance with a staging scheme. The gradual slow down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow down is gradual, the processor may flexibly avoid various degrees of livelock conditions. The mechanisms of the illustrative embodiments impact the overall processor performance based on the severity of the livelock condition by taking a small performance impact on less severe livelock conditions and only increasing the processor performance impact when the livelock condition is more severe.
摘要翻译：提供了将处理器置于逐渐减速操作模式的机制。逐渐减速操作模式包括处理器中的发行单元的减速操作的多个阶段，其中指令的发布根据分段方案变慢。处理器逐渐减速使处理器能够突破活动锁定状态。此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。说明性实施例的机制通过对较不严格的活锁状态采取小的性能影响，并且仅当活锁状态更严重时才增加处理器性能影响，基于活锁状态的严重性来影响整体处理器性能。

6. 发明申请

US20080016407A1 System and Method for Selectively Engaging Optional Data Reduction Mechanisms for Capturing Trace Data 有权
标题翻译：选择性地选择用于捕获跟踪数据的数据缩减机制的系统和方法
公开(公告)号：US20080016407A1
公开(公告)日：2008-01-17
申请号：US11457510
申请日：2006-07-14
申请人： Christopher M. Abernathy , Lydia M. Do , Ronald P. Hall , Michael L. Karm
发明人： Christopher M. Abernathy , Lydia M. Do , Ronald P. Hall , Michael L. Karm
IPC分类号： G06F11/00
CPC分类号： G06F11/3672
摘要： An on-chip trace engine stores trace data in on-chip trace arrays and routes the trace data to output pins. An external trace capture device captures the trace data. The on-chip trace engine streams the trace data through the debug output pins at a slower rate that can be supported by external trace capture device. If compression is insufficient for the required data rate reduction, the on-chip trace engine includes selectable data reduction mechanisms. Responsive to an overflow condition, meaning trace data is captured in on-chip trace arrays faster than it can be routed off chip, the on-chip trace engine enters an overflow mode in which one or more of the data reduction mechanisms are selected. The data reduction mechanisms may include, for example, a data width reduction component, a pattern match data elimination component, a priority source select component, an under-sampling component, or various combinations thereof.
摘要翻译：片上跟踪引擎将跟踪数据存储在片上跟踪数组中，并将跟踪数据路由到输出引脚。外部跟踪捕获设备捕获跟踪数据。片上跟踪引擎通过调试输出引脚以较慢的速率流式传输跟踪数据，可由外部跟踪捕获设备支持。如果压缩不足以减少所需的数据速率，则片上跟踪引擎包括可选择的数据缩减机制。响应于溢出条件，意味着跟踪数据在片上跟踪阵列中捕获的速度比芯片上路由速度更快，片上跟踪引擎进入溢出模式，其中选择一个或多个数据简化机制。数据减少机制可以包括例如数据宽度减少部件，模式匹配数据消除部件，优先级源选择部件，欠采样部件或其各种组合。

7. 发明授权

US08661227B2 Multi-level register file supporting multiple threads 失效
标题翻译：支持多线程的多级寄存器文件
公开(公告)号：US08661227B2
公开(公告)日：2014-02-25
申请号：US12884411
申请日：2010-09-17
申请人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
发明人： Christopher M. Abernathy , Mary D. Brown , Hung Q. Le , Dung Q. Nguyen
IPC分类号： G06F9/34
CPC分类号： G06F9/3851 , G06F9/30138
摘要： A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution.
摘要翻译：处理器包括指令提取单元，耦合到指令获取单元的发行队列，耦合到发行队列的执行单元，以及包括具有较低访问延迟的第一级寄存器文件和第二级寄存器文件的多级寄存器文件具有更高的访问延迟。第一级和第二级寄存器文件中的每一个包括用于保持多个线程同时共享的操作数的多个物理寄存器。处理器还包括映射器，在从指令获取单元向发布队列调度指定源逻辑寄存器的指令时，启动与第二级寄存器文件中的源逻辑寄存器相关联的第一操作数的交换，在第一级寄存器文件中保存的第二个操作数。在交换之后的问题队列向执行单元发出指令以执行。

8. 发明授权

US08099582B2 Tracking deallocated load instructions using a dependence matrix 有权
标题翻译：使用依赖矩阵跟踪取消分配的加载指令
公开(公告)号：US08099582B2
公开(公告)日：2012-01-17
申请号：US12410024
申请日：2009-03-24
申请人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.
摘要翻译：提供了一种跟踪取消分配的加载指令的机制。处理器检测发送队列中的一组指令中的加载指令是否已经丢失。响应于加载指令的未命中，指令调度器将加载指令分配给加载缺省队列，并从发出队列中释放加载指令。指令调度器确定在依赖矩阵的发布队列部分中是否存在用于加载指令的依赖条目。响应于依赖矩阵的发布队列部分中的加载指令的依赖条目的存在，指令调度器从依赖矩阵的发布队列部分的依赖条目读取数据，该依赖矩阵指定一组依赖的依赖指令在加载指令中，将数据写入依赖矩阵的加载未命中队列部分中的新条目。

9. 发明申请

US20110302392A1 INSTRUCTION TRACKING SYSTEM FOR PROCESSORS 失效
标题翻译：处理器指令跟踪系统
公开(公告)号：US20110302392A1
公开(公告)日：2011-12-08
申请号：US12793718
申请日：2010-06-04
申请人： Christopher M. Abernathy , Hung Q. Le , Dung Q. Nguyen , Benjamin W. Stolt
发明人： Christopher M. Abernathy , Hung Q. Le , Dung Q. Nguyen , Benjamin W. Stolt
IPC分类号： G06F9/30
CPC分类号： G06F9/3804 , G06F9/30 , G06F9/3851 , G06F9/3857
摘要： A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.
摘要翻译：一种用于跟踪处理器中的指令的方法和装置。处理器中的完成单元接收到添加到表中以形成接收到的指令组的指令组。响应于接收到接收到的指令组，完成单元确定是否存在包含在第一位置中的先前存储的指令组的条目，并且具有用于存储接收到的指令组的空间。响应于存在的条目，完成单元将接收到的指令组存储在条目中的第二位置，以形成存储的指令组。

10. 发明授权

US08046566B2 Method to reduce power consumption of a register file with multi SMT support 失效
标题翻译：减少具有多个SMT支持的寄存器文件功耗的方法
公开(公告)号：US08046566B2
公开(公告)日：2011-10-25
申请号：US12120958
申请日：2008-05-15
申请人： Christopher M. Abernathy , Jens Leenstra , Nicolas Maeding , Dung Quoc Nguyen
发明人： Christopher M. Abernathy , Jens Leenstra , Nicolas Maeding , Dung Quoc Nguyen
IPC分类号： G06F9/50 , G06F1/32
CPC分类号： G06F1/3203
摘要： A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system.
摘要翻译：公开了一种降低支持同时多线程（SMT）的微处理器的寄存器堆的功耗的方法。映射逻辑和关联的表条目监视当前在处理器和信号控制逻辑中执行的处理线程的总数，以禁用当前执行或挂起的指令线程所不需要的特定寄存器文件条目或使用最少的不满足最小访问阈值的寄存器文件条目最近使用的算法（LRU）。控制寄存器文件利用率，使得为未停用或将来的指令线程未分配选择用于去激活的寄存器文件地址范围。然后将一种或多种省电技术应用于禁用的寄存器文件，以减少系统中的总体功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式