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1. 发明授权

US07184450B1 System and method for decoding audio/video data such as DVD or/and DVB data 有权
标题翻译：用于解码诸如DVD或/和DVB数据的音频/视频数据的系统和方法
公开(公告)号：US07184450B1
公开(公告)日：2007-02-27
申请号：US09301438
申请日：1999-04-28
申请人： Christopher K. Wolf , Ygal Arbel , Himanshu A. Sanghavi
发明人： Christopher K. Wolf , Ygal Arbel , Himanshu A. Sanghavi
IPC分类号： H04J3/04 , H04L12/28 , H04N5/91 , H04N5/262
CPC分类号： H04N21/434 , G11B20/10 , G11B20/10527 , G11B20/1403 , G11B27/3027 , G11B2020/10685 , G11B2020/10694 , G11B2220/2562 , H04J3/0638 , H04L69/12 , H04N21/23406 , H04N21/2368 , H04N21/42607 , H04N21/4341 , H04N21/44004
摘要： A system (20) for decoding a data stream allocated into data packets contains a control unit (54), a stream demultiplexer (26), audio and video decoders (38 and 40), a memory management unit (60), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.
摘要翻译：用于解码分配到数据分组中的数据流的系统（20）包括控制单元（54），流解复用器（26），音频和视频解码器（38和40），存储器管理单元（60）视频输入和输出缓冲区。在不中断控制单元的情况下对数据分组进行解复用和解封装，解复用器将编码的音频和视频数据发送到音频和视频输入缓冲器。视频消息处理视频定时信息并识别编码视频数据存储在视频输入缓冲器中的位置由解复用器提供，供控制单元使用。利用从控制单元提供的相应的视频指令，视频解码器解码编码的视频数据，产生提供给视频输出缓冲器的解码视频数据。音频解码器解码编码的音频数据以产生提供给音频输出缓冲器的解码音频数据。存储器管理单元控制向/从音频输出缓冲器的解码音频数据的传送。

2. 发明授权

US07852408B2 Fractional phase-locked loop for generating high-definition and standard-definition reference clocks 有权
标题翻译：用于生成高清晰度和标准清晰度参考时钟的分数锁相环
公开(公告)号：US07852408B2
公开(公告)日：2010-12-14
申请号：US11383551
申请日：2006-05-16
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： H04N5/06 , H04N5/46 , H04N9/45 , H04N9/455 , H03L7/85 , H03L7/89 , H03L7/06 , H03L7/26 , H03B1/00
CPC分类号： H03L7/1974 , G09G5/18 , H03L7/23 , H04N5/46 , H04N21/4305
摘要： A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.
摘要翻译：公开了一种可编程分数锁相环，用于产生一个148.50000 MHz高清电视参考时钟和一个来自27 MHz晶体的148.35164 MHz高清参考时钟。为了产生148.50000 MHz参考时钟，分数锁相环乘以11/2，并产生148.35164 MHz参考时钟，分数锁相环乘以500/91。然而，在分数相锁定环内部，分数11/2由分母为二分之一表示，分数500/91由分母为91的整数倍表示。

3. 发明申请

US20060230052A1 Compact and hitlessly-resizable multi-channel queue 审中-公开
标题翻译：紧凑和无限大小的多渠道队列
公开(公告)号：US20060230052A1
公开(公告)日：2006-10-12
申请号：US11103978
申请日：2005-04-12
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： G06F7/00
CPC分类号： G06F5/065 , G06F2205/063 , G06F2205/066
摘要： A queue is disclosed (i) that provides for single-channel and multi-channel operation and that can change between single-channel and multi-channel operation during operation hitlessly, (ii) in which the number of channels and each channel's size can be changed during operation hitlessly, and (iii) is compact. To accomplish this, the illustrative embodiment comprises a group of doubly-linked lists, one for each channel's storage. One set of links indicates the node where the next datum is to be written and the other set of links indicates the node where the next datum is to be read. By bifurcating each channel's queue into a set of write links and read links, the illustrative embodiment can resize a channel during operation hitlessly.
摘要翻译：公开了一种队列（i），其提供单通道和多通道操作，并且可以在无效操作期间在单通道和多通道操作之间改变，（ii）其中通道数量和每个通道的尺寸可以是在运行中无效地改变，（iii）是紧凑的。为了实现这一点，说明性实施例包括一组双向链表，每个通道的存储一个。一组链接指示下一个数据要被写入的节点，另一组链接指示要读取下一个数据的节点。通过将每个通道的队列分成一组写入链接和读取链接，所述说明性实施例可以在无效的操作期间调整通道的大小。

4. 发明申请

US20070268405A1 Fractional Phase-Locked Loop for Generating High-Definition and Standard-Definition Reference Clocks 有权
标题翻译：用于生成高清晰度和标准清晰度参考时钟的分数锁相环
公开(公告)号：US20070268405A1
公开(公告)日：2007-11-22
申请号：US11383551
申请日：2006-05-16
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： H03L7/00 , H03B19/00
CPC分类号： H03L7/1974 , G09G5/18 , H03L7/23 , H04N5/46 , H04N21/4305
摘要： A programmable fractional phase-locked loop for generating a 148.50000 MHz high-definition television reference clock and a 148.35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148.50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148.35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.
摘要翻译：公开了一种可编程分数锁相环，用于产生一个148.50000 MHz高清电视参考时钟和一个来自27 MHz晶体的148.35164 MHz高清参考时钟。为了产生148.50000 MHz参考时钟，分数锁相环乘以11/2，并产生148.35164 MHz参考时钟，分数锁相环乘以500/91。然而，在分数相锁定环内部，分数11/2由分母为二分之一表示，分数500/91由分母为91的整数倍表示。

5. 发明授权

US6002441A Audio/video subprocessor method and structure 失效
标题翻译：音频/视频子处理器的方法和结构
公开(公告)号：US6002441A
公开(公告)日：1999-12-14
申请号：US742583
申请日：1996-10-28
申请人： Hemant Bheda , Ygal Arbel , Partha Srinivasan
发明人： Hemant Bheda , Ygal Arbel , Partha Srinivasan
IPC分类号： H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/4143 , H04N21/434 , H04N7/32
CPC分类号： H04N21/4143 , H04N19/42 , H04N19/61 , H04N21/4341 , H04N21/439 , H04N21/44
摘要： A novel method and apparatus for decoding a compressed audio/video signal to produce decoded audio and decoded video signals. The decoding tasks are partitioned into "pre-processing tasks" and "post-processing tasks." Pre-processing tasks involve one or more non-signal processing oriented operations which do not require extensive computing resources. Pre-processing tasks are assigned to be executed by the host processor, which can perform these tasks without straining it computational resources. Pre-processing tasks include demultiplexing the compressed audio/video stream into compressed audio and compressed video streams, performing audio pre-processing on the compressed audio stream and performing video pre-processing on the compressed video stream. Post-processing tasks involve one or more signal processing oriented operations which require extensive computing resources. Pre-processing tasks are assigned to be executed by a dedicated subprocessor. Post-processing tasks include audio post-processing and video post-processing. In an embodiment, video frame tasks are also performed as part of video post-processing. Post-processing performed by the dedicated subprocessor outputs a decoded audio signal and a decoded video signal.
摘要翻译：一种用于解码压缩音频/视频信号以产生解码音频和解码视频信号的新颖方法和装置。解码任务分为“预处理任务”和“后处理任务”。预处理任务涉及不需要大量计算资源的一个或多个非信号处理导向操作。分配预处理任务将由主机处理器执行，主处理器可以执行这些任务而不使其计算资源变紧。预处理任务包括将压缩音频/视频流解复用为压缩音频和压缩视频流，对压缩音频流执行音频预处理，并在压缩视频流上执行视频预处理。后处理任务涉及需要大量计算资源的一个或多个面向信号处理的操作。分配预处理任务由专用子处理器执行。后处理任务包括音频后处理和视频后处理。在一个实施例中，视频帧任务也作为视频后处理的一部分执行。由专用子处理器执行的后处理输出解码音频信号和解码视频信号。

6. 发明授权

US4912758A Full-duplex digital speakerphone 失效
标题翻译：全双工数字扬声器
公开(公告)号：US4912758A
公开(公告)日：1990-03-27
申请号：US263115
申请日：1988-10-26
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： H04M1/60 , H04B3/23 , H04M9/08
CPC分类号： H04M9/082
摘要： A full-duplex digital speakerphone 10 includes a transmit signal path having an output coupled to a telephone trunk and a receive signal path having an input coupled to the telephone trunk and an output coupled to a loudspeaker. The speakerphone further includes a room echo cancellation adaptive filter 56 and a trunk echo cancellation adaptive filter 66. Serially coupled within the transmit signal path is a selective suppression block 50 for suppressing a component of a Mu-Law or an A-Law quantization error signal. A second selective suppression block 52 is serially coupled within the receive signal path. Suppression of non-linearities due to Mu-Law or A-Law signal conversion is also accommodated by providing a non-linear signal processing block 40 at an input to an adaptive filter and an optional non-linear signal processing block at an output of the adaptive filter. Each of the blocks emulates and compensates for signal converter non-linearity. The speakerphone facilitates adaptive filter coefficient initialization by beginning a call in a half-duplex mode and switching to full-duplex when filter coefficients are adapted. The speakerphone also has a variable adaptation step size which is a function of a short-term estimate of signal power within the associated transmit or receive signal paths.

7. 发明授权

US07184662B2 Switching network 有权
标题翻译：切换网络
公开(公告)号：US07184662B2
公开(公告)日：2007-02-27
申请号：US09974448
申请日：2001-10-10
申请人： Ygal Arbel , Robert Louis Caulk , Christoph Dominique Loeffler-Lejeune
发明人： Ygal Arbel , Robert Louis Caulk , Christoph Dominique Loeffler-Lejeune
IPC分类号： H04J14/00
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/001 , H04J2203/0025
摘要： A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.
摘要翻译：一个两级交换网络，从一个输入端接收数据，并首先将其通过一个空间级切换到一个缓冲区。然后将来自缓冲器的数据在时空阶段切换到输出。每个缓冲器有利地保持一帧数据。此外，存在两个缓冲器，使得可以从输入填充另一个缓冲器，而另一个缓冲器被排空到输出端，反之亦然。无论其来源和目的地如何，最大数量的数据可以在空间和时间上进行切换，从而实现能够达到最大SONET指定带宽的交换网络。

8. 发明申请

US20070025732A1 SWITCHING NETWORK 有权
标题翻译：切换网络
公开(公告)号：US20070025732A1
公开(公告)日：2007-02-01
申请号：US09974448
申请日：2001-10-10
申请人： Ygal Arbel , Robert Caulk , Christoph Loeffler-Lejeune
发明人： Ygal Arbel , Robert Caulk , Christoph Loeffler-Lejeune
IPC分类号： H04J14/00
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/001 , H04J2203/0025
摘要： A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.
摘要翻译：一个两级交换网络，从一个输入端接收数据，并首先将其通过一个空间级切换到一个缓冲区。然后将来自缓冲器的数据在时空阶段切换到输出。每个缓冲器有利地保持一帧数据。此外，存在两个缓冲器，使得可以从输入填充另一个缓冲器，而另一个缓冲器被排空到输出端，反之亦然。无论其来源和目的地如何，最大数量的数据可以在空间和时间上进行切换，从而实现能够达到最大SONET指定带宽的交换网络。

9. 发明授权

US06282631B1 Programmable RISC-DSP architecture 有权
标题翻译：可编程RISC-DSP架构
公开(公告)号：US06282631B1
公开(公告)日：2001-08-28
申请号：US09220158
申请日：1998-12-23
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： G06F1500
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/34 , G06F9/345 , G06F9/3455 , G06F9/3879 , G06F15/7857
摘要： The present invention provides an audio signal processor and method of operation thereof that enables efficient digital signal processing. Fast multiply-accumulate (MAC) and vector processing capabilities are implemented in a RISC architecture giving the high speed capabilities of a digital signal processing system the speed and efficiency of a RISC processor.
摘要翻译：本发明提供一种能够实现高效数字信号处理的音频信号处理器及其操作方法。快速乘法累加（MAC）和矢量处理能力在RISC架构中实现，为数字信号处理系统的高速能力提供了RISC处理器的速度和效率。

10. 发明授权

US5982935A Method and apparatus for computing MPEG video reconstructed DCT coefficients 失效
标题翻译：用于计算MPEG视频重构DCT系数的方法和装置
公开(公告)号：US5982935A
公开(公告)日：1999-11-09
申请号：US834059
申请日：1997-04-11
申请人： Ygal Arbel
发明人： Ygal Arbel
IPC分类号： G06T9/00 , H04N7/26 , H04N7/30 , G06K9/36 , G06K9/46 , H04N1/415
CPC分类号： H04N19/45 , H04N19/60
摘要： A novel apparatus and method is disclosed to perform discrete cosine transform (DCT) coefficient reconstruction more efficiently and using less hardware resources than prior art techniques. The invention comprises a correction factor generator apparatus which computes a correction factor which is used in the DCT coefficient reconstruction process. Use of the correction factor enables DCT coefficient reconstruction to be performed using lesser computations and lesser hardware resources than prior art techniques. The apparatus and method can be used to perform DCT coefficient reconstruction for both MPEG-1 and MPEG-2 encoded video data streams.
摘要翻译：公开了一种新颖的装置和方法，以更有效地执行离散余弦变换（DCT）系数重建，并且比现有技术使用更少的硬件资源。本发明包括一个校正因子发生器装置，该装置计算在DCT系数重建过程中使用的校正因子。使用校正因子使得能够使用比现有技术更少的计算和较少的硬件资源来执行DCT系数重构。该装置和方法可用于对MPEG-1和MPEG-2编码视频数据流进行DCT系数重构。

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