专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07469399B2 Semi-flattened pin optimization process for hierarchical physical designs 失效
标题翻译：半平面针脚优化过程，用于分层物理设计
公开(公告)号：US07469399B2
公开(公告)日：2008-12-23
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问。

2. 发明申请

US20080066039A1 Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs 失效
标题翻译：用于分层物理设计的半平面针优化过程
公开(公告)号：US20080066039A1
公开(公告)日：2008-03-13
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问

3. 发明申请

US20080301614A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR SPARE CIRCUITRY DISTRIBUTION 审中-公开
标题翻译：方法，系统和计算机程序产品用于备用电路分配
公开(公告)号：US20080301614A1
公开(公告)日：2008-12-04
申请号：US11757465
申请日：2007-06-04
申请人： Eddy St. Juste , Moussadek Belaidi
发明人： Eddy St. Juste , Moussadek Belaidi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system, and computer program product for spare circuitry distribution in an integrated circuit design are provided. The method includes receiving design data for the integrated circuit design. The design data includes descriptions of spare circuitry and physical area available for circuitry placement. The method further includes determining target placement locations for the spare circuitry, where the target placement locations create a balanced distribution of the spare circuitry throughout the physical area available for circuitry placement. The method also includes shifting the location of the spare circuitry from each target placement location towards a nearest clock block within the integrated circuit design, resulting in an updated integrated circuit design. The method additionally includes outputting the updated integrated circuit design.
摘要翻译：提供了一种用于集成电路设计中的备用电路分配的方法，系统和计算机程序产品。该方法包括接收集成电路设计的设计数据。设计数据包括可用于电路放置的备用电路和物理区域的描述。该方法还包括确定备用电路的目标放置位置，其中目标放置位置在可用于电路放置的整个物理区域中创建备用电路的平衡分布。该方法还包括将备用电路的位置从集成电路设计中的每个目标放置位置移向最近的时钟块，从而得到更新的集成电路设计。该方法还包括输出更新的集成电路设计。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式