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1. 发明申请

US20080066039A1 Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs 失效
标题翻译：用于分层物理设计的半平面针优化过程
公开(公告)号：US20080066039A1
公开(公告)日：2008-03-13
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问

2. 发明授权

US08122400B2 Logic difference synthesis 有权
标题翻译：逻辑差分合成
公开(公告)号：US08122400B2
公开(公告)日：2012-02-21
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

3. 发明申请

US20110004857A1 LOGIC DIFFERENCE SYNTHESIS 有权
标题翻译：逻辑差异综合
公开(公告)号：US20110004857A1
公开(公告)日：2011-01-06
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

4. 发明授权

US08103989B2 Method and system for changing circuits in an integrated circuit 有权
标题翻译：用于改变集成电路中的电路的方法和系统
公开(公告)号：US08103989B2
公开(公告)日：2012-01-24
申请号：US12037421
申请日：2008-02-26
申请人： Nathan A. Dotson , Jonathan Y. Chen , David L. Rude , Vern A. Victoria
发明人： Nathan A. Dotson , Jonathan Y. Chen , David L. Rude , Vern A. Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage.
摘要翻译：提供了一种用于修改集成电路和集成电路的方法。该方法包括：提供包括具有第一阈值电压的多个电路簿的集成电路设计; 以及用具有低于第一阈值电压的第二阈值电压的至少一个门阵列簿代替多个电路簿中的至少一个。

5. 发明申请

US20090212819A1 METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于在集成电路中更改电路的方法和系统
公开(公告)号：US20090212819A1
公开(公告)日：2009-08-27
申请号：US12037421
申请日：2008-02-26
申请人： Nathan A. Dotson , Jonathan Y. Chen , David L. Rude , Vern A. Victoria
发明人： Nathan A. Dotson , Jonathan Y. Chen , David L. Rude , Vern A. Victoria
IPC分类号： H01L25/00 , G06F17/50
CPC分类号： G06F17/505
摘要： A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage.
摘要翻译：提供了一种用于修改集成电路和集成电路的方法。该方法包括：提供包括具有第一阈值电压的多个电路簿的集成电路设计; 以及用具有低于第一阈值电压的第二阈值电压的至少一个门阵列簿代替多个电路簿中的至少一个。

6. 发明授权

US07469399B2 Semi-flattened pin optimization process for hierarchical physical designs 失效
标题翻译：半平面针脚优化过程，用于分层物理设计
公开(公告)号：US07469399B2
公开(公告)日：2008-12-23
申请号：US11531398
申请日：2006-09-13
申请人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
发明人： Christopher J. Berry , Christopher M. Carney , David L. Rude , Eddy St. Juste
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
摘要翻译：在由多个宏功能逻辑块组成的分层半导体数字单元中，每个所述宏功能逻辑块由多个叶单元组成，每个所述叶单元经由输入端和输出端访问，其中定位每个输入终端提供对靠近输入终端提供访问的叶单元的合法位置处的单个叶单元的访问。

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