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1. 发明授权

US5826070A Apparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unit 失效
标题翻译：用于在有序的浮点执行单元中使用重命名技术来维护状态标志和条件代码的装置和方法
公开(公告)号：US5826070A
公开(公告)日：1998-10-20
申请号：US708006
申请日：1996-08-30
申请人： Christopher Hans Olson , Jeffrey Scott Brooks , Martin Stanley Schmookler
发明人： Christopher Hans Olson , Jeffrey Scott Brooks , Martin Stanley Schmookler
IPC分类号： G06F9/32 , G06F9/38 , G06F9/302
CPC分类号： G06F9/3855 , G06F9/30094 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3853 , G06F9/3857
摘要： An apparatus and method reduces the number of rename registers for a floating point status and control register (FPSCR) in a superscalar microprocessor executing out of order/speculative instructions. A floating point queue (FPQ) receives speculative instructions and issues out-of-order instructions to FPQ execution units, each instruction containing a group identifier tag (GID) and a target identifier tag (TID). The GID tag indicates a set of instructions bounded by interruptible or branch instructions. The TID indicates a targeted architected facility and the program order of the instruction. The FPSCR contains status and control bits for each instruction and is updated when an instruction is executed and committed. A FPSCR renaming mechanism assigns an FPSCR rename to selected FPSCR bits during instruction dispatch from an instruction fetch unit (IFU) to the FPQ when an arithmetic instruction is dispatched that has a GID which has not been committed by instruction dispatch unit (IDU) and does not already have an FPSCR rename assigned, as determined by the FPQ. The FPSCR rename mechanism utilizes the TID upon the presence of selected bits in the FPSCR. The bits in the FPSCR rename are updated as a new arithmetic instruction enters a write-back stage in the FPU. The resulting FPSCR updates of all instructions in a given GID are merged into one FPSCR rename register. A FPSCR rename register exists for each GID rather than a FPSCR rename register for each FPR rename register as in the prior art.
摘要翻译：一种装置和方法减少了执行无序/推测性指令的超标量微处理器中浮点状态和控制寄存器（FPSCR）的重命名寄存器的数量。浮点队列（FPQ）接收推测指令并向FPQ执行单元发出无序指令，每个指令包含组标识符标签（GID）和目标标识符标签（TID）。 GID标签指示一组由可中断或分支指令限定的指令。 TID表示目标架构设施和指令的程序顺序。 FPSCR包含每条指令的状态和控制位，并在指令执行并提交时更新。当调度具有尚未由指令分派单元（IDU）提交的GID的算术指令时，FPSCR重命名机制在从指令获取单元（IFU）到FPQ的指令分派期间将FPSCR重命名分配给所选择的FPSCR位，并且尚未由FPQ确定的FPSCR重命名分配。 FPSCR重命名机制在FPSCR中存在选定位时利用TID。 FPSCR重命名中的位随着新的算术指令进入FPU中的回写阶段而被更新。给定GID中的所有指令的结果FPSCR更新被合并到一个FPSCR重命名寄存器中。对于每个GID而言，对于每个FPR重命名寄存器，存在针对每个GID的FPSCR重命名寄存器，如现有技术中那样。

2. 发明授权

US5790444A Fast alignment unit for multiply-add floating point unit 失效
标题翻译：用于多重加法浮点单元的快速对准单元
公开(公告)号：US5790444A
公开(公告)日：1998-08-04
申请号：US727331
申请日：1996-10-08
申请人： Christopher Hans Olson , Martin Stanley Schmookler
发明人： Christopher Hans Olson , Martin Stanley Schmookler
IPC分类号： G06F5/01 , G06F7/544 , G06F7/00 , G06F7/38
CPC分类号： G06F7/5443 , G06F5/012 , G06F7/483
摘要： A floating point arithmetic unit performs a multiply-add function B+(A*C) in which an alignment shifter is responsive to an input signal representative of the B mantissa. The shifter includes a sequential stack of multiplexers, typically three (3), for shifting the B mantissa to align it with the A*C product, and a complementer contained between two of the multiplexers to invert the signals when B is a negative number. A shift amount generator responsive to the A, B and C exponents produces control signals for the multiplexers. The shift amount generator includes a multiple input adder utilizing carry save adder and carry lookahead adder techniques to minimize delay, and separate decoders for each multiplexer or group of multiplexers. The generator also includes a Leading Zeros Anticipator (LZA) circuit for the most significant bits to limit shift amount signals that are within the shifting range of the shifter, which reduces the delay attributed to the carry lookahead adder. The multiplexers are arranged in a sequence such that the control signals for the first multiplexers are dependent only on the least significant bits and thus can be generated earliest, and therefore the delay of these multiplexers and the delay of the complementer is in parallel with the delay for producing the control signals to the last multiplexers.
摘要翻译：浮点算术单元执行其中对准移位器响应于代表B尾数的输入信号的加法函数B +（A * C）。移位器包括一组多路复用器，通常为三（3），用于移位B尾数以将其与A * C乘积对齐，以及包含在两个多路复用器之间的补码器，以在B为负数时反转信号。响应于A，B和C指数的移位量发生器产生用于多路复用器的控制信号。移位量产生器包括利用进位存储加法器和进位前置加法器技术来最小化延迟的多输入加法器，以及用于每个多路复用器或多路复用器组的单独解码器。该发生器还包括一个用于最高有效位的前导零点预期器（LZA）电路，用于限制在移位器的移位范围内的移位量信号，这减少了归因于进位前瞻加法器的延迟。多路复用器按照这样的顺序排列，使得用于第一多路复用器的控制信号仅依赖于最低有效位，并且因此可以最早生成，因此这些多路复用器的延迟和补码器的延迟与延迟并行用于产生到最后一个多路复用器的控制信号。

3. 发明授权

US6032249A Method and system for executing a serializing instruction while bypassing a floating point unit pipeline 失效
标题翻译：在绕过浮点单元流水线的同时执行串行化指令的方法和系统
公开(公告)号：US6032249A
公开(公告)日：2000-02-29
申请号：US16981
申请日：1998-02-02
申请人： Christopher Hans Olson , Jeffrey Scott Brooks
发明人： Christopher Hans Olson , Jeffrey Scott Brooks
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/3857
摘要： A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The processor includes execution logic having a pipeline for executing the nonserializing instruction. The processor also includes logic separate from the execution logic for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic. The serializing instruction is executed without providing the serializing instruction to the pipeline.
摘要翻译：公开了一种用于在处理器中直接执行串行化指令的方法和系统。处理器具有串行化指令和非串行化指令。处理器包括具有用于执行非串行化指令的流水线的执行逻辑。处理器还包括与用于执行串行化指令的执行逻辑分离的逻辑。该方法和系统包括识别串行化指令，识别非串行化指令，向执行逻辑提供非串行化指令，以及向单独逻辑提供串行化指令。在不向流水线提供串行化指令的情况下执行串行化指令。

4. 发明授权

US5961636A Checkpoint table for selective instruction flushing in a speculative execution unit 失效
标题翻译：用于在推测执行单元中进行选择性指令刷新的检查点表
公开(公告)号：US5961636A
公开(公告)日：1999-10-05
申请号：US934960
申请日：1997-09-22
申请人： Jeffrey Scott Brooks , Hoichi Cheong , Tiberiu Carol Galambos , Christopher Hans Olson
发明人： Jeffrey Scott Brooks , Hoichi Cheong , Tiberiu Carol Galambos , Christopher Hans Olson
IPC分类号： G06F9/38 , G06F9/302
CPC分类号： G06F9/3842 , G06F9/3863
摘要： In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.
摘要翻译：在具有将浮点指令分派到浮点单元的处理器的数据处理系统中，检查点表与浮点寄存器重命名表相关联，用于在发生错误预测的分支时恢复浮点寄存器重命名表的状态或中断。这完成了（1）使用与每个指令相关联的程序命令标签，（2）通过将浮点寄存器重命名表的有效位向量与其程序命令标签为所有检查点条目中最古老的程序订单标签与错误预测的分支或中断的指令的程序订单标签更年轻或更旧，以及（3）通过使用检查点条目的位置部分来替换寄存器的NEXT指针重命名表。

5. 发明授权

US5878242A Method and system for forwarding instructions in a processor with increased forwarding probability 失效
标题翻译：用于在具有增加的转发概率的处理器中转发指令的方法和系统
公开(公告)号：US5878242A
公开(公告)日：1999-03-02
申请号：US845093
申请日：1997-04-21
申请人： Christopher Hans Olson , Jeffrey Scott Brooks
发明人： Christopher Hans Olson , Jeffrey Scott Brooks
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3826
摘要： A system and method for forwarding a first instruction into a second instruction in a processor is disclosed. The processor comprises an execution unit and providing a plurality of instructions. The first instruction depends upon execution of the second instruction but does not otherwise require execution by the execution unit. The method first searches for the second instruction. The method then forwards the first instruction via the second instruction by appending a tag to the second instruction, the tag identifying the first instruction.One aspect of the method and system forwards a store instruction into a floating point instruction in a processor. The store instruction has a source address and the floating point instruction has a target address. The processor provides a plurality of instructions. The method searches for the floating point instruction that is provided before the store instruction. The method then determines if the source address is equal to the target address. The method forwards the store instruction through the floating point instruction if the source address is equal to the target address by appending a tag to the floating point instruction, the tag identifying the store instruction.
摘要翻译：公开了一种用于将第一指令转发到处理器中的第二指令的系统和方法。处理器包括执行单元并提供多个指令。第一条指令取决于第二条指令的执行，但是否则不需要执行单元的执行。该方法首先搜索第二条指令。然后，该方法通过将标签附加到第二指令，通过第二指令转发第一指令，标签识别第一指令。该方法和系统的一个方面将存储指令转发到处理器中的浮点指令。存储指令具有源地址，浮点指令具有目标地址。处理器提供多个指令。该方法搜索在存储指令之前提供的浮点指令。该方法然后确定源地址是否等于目标地址。如果源地址等于目标地址，则该方法通过将浮点指令附加到浮点指令（标识存储指令）的标记来转发存储指令。

6. 发明授权

US06484251B1 Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor 失效
标题翻译：基于无序处理器中的指令提交，基于设置/清除对中的指令特定修改信息更新状态寄存器
公开(公告)号：US06484251B1
公开(公告)日：2002-11-19
申请号：US09417824
申请日：1999-10-14
申请人： Robert Greg McDonald , Peichun Peter Liu , Christopher Hans Olson
发明人： Robert Greg McDonald , Peichun Peter Liu , Christopher Hans Olson
IPC分类号： G06F938
CPC分类号： G06F9/3865 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A processor including a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function circuit is configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. The commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.
摘要翻译：一种包括寄存器，执行单元，临时结果缓冲器和提交函数电路的处理器。寄存器包括至少一个寄存器位，并且可以包括一个或多个粘性位。执行单元适用于执行一组计算机指令。临时结果缓冲器被配置为从执行单元接收由指令提供的寄存器位修改信息。临时结果缓冲器适用于将修改信息存储在与寄存器的各个寄存器位对应的置位/清除位中。提交函数电路被配置为在提交指令时从临时结果缓冲器接收置位/清除的位对。提交函数电路适于响应于接收到置位/清除位对而产生更新的位。更新的位然后被提交到寄存器的相应寄存器位。

7. 发明授权

US5790445A Method and system for performing a high speed floating point add operation 失效
标题翻译：执行高速浮点加法运算的方法和系统
公开(公告)号：US5790445A
公开(公告)日：1998-08-04
申请号：US641307
申请日：1996-04-30
申请人： Lee Evan Eisen , Timothy Alan Elliott , Robert Thaddeus Golla , Christopher Hans Olson
发明人： Lee Evan Eisen , Timothy Alan Elliott , Robert Thaddeus Golla , Christopher Hans Olson
IPC分类号： G06F5/01 , G06F7/485 , G06F7/50 , G06F7/38
CPC分类号： G06F7/485 , G06F5/012
摘要： A system and method for calculating a floating point add/subtract of a plurality of floating point operands is disclosed. The system comprises at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path includes a first aligner, a first adder coupled to the first aligner, and a first normalizer coupled to the first adder. The first normalizer is capable of shifting a mantissa by a substantially smaller number of digits than the first aligner. The second data path comprises control logic, a second aligner coupled to the control logic, a second adder coupled to the second aligner, and a second normalizer coupled to the second adder. The control logic provides a control signal that is responsive to a first predetermined number of digits of each exponent of a pair of exponents. The pair of exponents are the exponents for a pair of inputs to the second data path. The second aligner is responsive to the control signal provided by the control logic. In addition, the second normalizer is capable of shifting a mantissa by a substantially larger number of digits than the second aligner.
摘要翻译：公开了一种用于计算多个浮点操作数的浮点加法/减法的系统和方法。该系统包括至少一对数据路径。每对数据路径包括第一数据路径和第二数据路径。第一数据路径包括第一对准器，耦合到第一对准器的第一加法器和耦合到第一加法器的第一归一化器。第一标准器能够将尾数移位比第一对准器小得多的位数。第二数据路径包括控制逻辑，耦合到控制逻辑的第二对准器，耦合到第二对准器的第二加法器以及耦合到第二加法器的第二归一化器。控制逻辑提供响应于一对指数的每个指数的第一预定数量位数的控制信号。一对指数是对于第二数据路径的一对输入的指数。第二对准器响应于由控制逻辑提供的控制信号。此外，第二归一化器能够将尾数移动比第二对准器大得多的位数。

8. 发明授权

US5943494A Method and system for processing multiple branch instructions that write to count and link registers 失效
标题翻译：用于处理写入计数和链接寄存器的多个分支指令的方法和系统
公开(公告)号：US5943494A
公开(公告)日：1999-08-24
申请号：US486304
申请日：1995-06-07
申请人： Robert Thaddeus Golla , Christopher Hans Olson
发明人： Robert Thaddeus Golla , Christopher Hans Olson
IPC分类号： G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/30061 , G06F9/3842 , G06F9/3863
摘要： A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system comprises an architected count register and an architected link register that are each connected to a look-ahead register. Information in the architected count or link register is copied into the look-ahead register when a branch instruction is encountered that will alter the contents of the count or link registers. Information in the look-ahead register is saved in a shadow register when an unresolved branch is encountered, and restored by the shadow register if the outcome of the unresolved branch is mispredicted.
摘要翻译：用于处理计数和链接分支指令的系统和方法，其允许多个分支在同一时间未完成，而不限于分配给计数和链接寄存器的重命名寄存器的数量。该方法和系统包括各自连接到预先注册的架构计数寄存器和架构的链接寄存器。当遇到将改变计数或链接寄存器的内容的分支指令时，将结构计数或链接寄存器中的信息复制到预读寄存器中。当遇到未解决的分支时，预览寄存器中的信息保存在影子寄存器中，如果未解析的分支的结果被错误预测，则由影子寄存器还原。

9. 发明授权

US5802346A Method and system for minimizing the delay in executing branch-on-register instructions 失效
标题翻译：用于最小化执行分支指令指令的延迟的方法和系统
公开(公告)号：US5802346A
公开(公告)日：1998-09-01
申请号：US457714
申请日：1995-06-02
申请人： Robert Thaddeus Golla , Christopher Hans Olson
发明人： Robert Thaddeus Golla , Christopher Hans Olson
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/322 , G06F9/3824
摘要： A system and method for minimizing the delay associated with executing a register dependent instruction in which the execution of the register dependent instruction is dependent on an operand of a preceding instruction. In a branch unit for executing register dependent instructions, functional units are connected via a rename bus, and the functional units are connected to a general purpose register (GPR) via a GPR bus. The system and method routes the rename bus and the GPR bus directly to an instruction fetch address register thereby enabling the branch unit to execute a register dependent instruction during the same cycle as the preceding instruction.
摘要翻译：一种用于最小化与执行依赖于寄存器的指令相关联的延迟的系统和方法，其中执行依赖于寄存器的指令取决于前一指令的操作数。在用于执行与寄存器有关的指令的分支单元中，功能单元经由重命名总线连接，功能单元通过GPR总线连接到通用寄存器（GPR）。系统和方法将重命名总线和GPR总线直接传送到指令获取地址寄存器，从而使分支单元在与前一指令相同的周期内执行与寄存器相关的指令。

10. 发明授权

US5880983A Floating point split multiply/add system which has infinite precision 失效
标题翻译：具有无限精度的浮点分割乘法/加法系统
公开(公告)号：US5880983A
公开(公告)日：1999-03-09
申请号：US620733
申请日：1996-03-25
申请人： Timothy Alan Elliott , Robert Thaddeus Golla , Christopher Hans Olson , Terence Matthew Potter
发明人： Timothy Alan Elliott , Robert Thaddeus Golla , Christopher Hans Olson , Terence Matthew Potter
IPC分类号： G06F7/544 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49942
摘要： A method and system for an infinite precision split multiply and add operation which has increased speed. The method and system for providing a split multiply and add of a plurality of operands include a multiplier and an adder means. The multiplier multiplies a first portion of the plurality of operands, thereby providing a product. The adder, which combines the remaining operands and the product, comprise at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path comprises a first aligner, a first adder, and a first normalizer capable of shifting a mantissa by a substantially fewer number digits than the aligner. The second data path comprises a second aligner, a second adder, and a second normalizer capable of shifting a mantissa by a substantially larger number of digits than the aligner. Accordingly, the present invention includes split multiply and add data paths which, individually, are faster than a fused multiply and add. In addition, the split multiply and add data paths can preserve the appearance of infinite precision. Consequently, overall system performance is increased.
摘要翻译：一种用于无限精密分割乘法和加法运算的方法和系统，其具有增加的速度。用于提供多个操作数的分割乘法和相加的方法和系统包括乘法器和加法器装置。乘法器乘以多个操作数的第一部分，从而提供乘积。组合剩余操作数和乘积的加法器包括至少一对数据路径。每对数据路径包括第一数据路径和第二数据路径。第一数据路径包括第一对准器，第一加法器和第一归一化器，其能够将尾数与对准器相比更少的数字位移。第二数据路径包括第二对准器，第二加法器和第二归一化器，其能够将尾数移位比对准器大得多的位数。因此，本发明包括分离的乘法和加法数据路径，其分别比融合乘法和加法更快。此外，拆分乘法和添加数据路径可以保持无限精度的外观。因此，整体系统性能提高。

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