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1. 发明授权

US5961636A Checkpoint table for selective instruction flushing in a speculative execution unit 失效
标题翻译：用于在推测执行单元中进行选择性指令刷新的检查点表
公开(公告)号：US5961636A
公开(公告)日：1999-10-05
申请号：US934960
申请日：1997-09-22
申请人： Jeffrey Scott Brooks , Hoichi Cheong , Tiberiu Carol Galambos , Christopher Hans Olson
发明人： Jeffrey Scott Brooks , Hoichi Cheong , Tiberiu Carol Galambos , Christopher Hans Olson
IPC分类号： G06F9/38 , G06F9/302
CPC分类号： G06F9/3842 , G06F9/3863
摘要： In a data processing system having a processor, which dispatches floating point instructions to a floating point unit, a checkpoint table is associated with a floating point register rename table for restoring the state of the floating point register rename table upon the occurrence of a mispredicted branch or an interrupt. This is accomplished (1) using a program order tag associated with each one of the instructions, (2) by replacing the valid bit vector of the floating point register rename table with the valid bit vector of a checkpoint entry whose program order tag is the oldest among all checkpoint entries that have a program order tag younger or as old as the program order tag of the mispredicted branch or the interrupted instruction, and (3) by using the location portion of the checkpoint entry to replace the NEXT pointer of the register renaming table.
摘要翻译：在具有将浮点指令分派到浮点单元的处理器的数据处理系统中，检查点表与浮点寄存器重命名表相关联，用于在发生错误预测的分支时恢复浮点寄存器重命名表的状态或中断。这完成了（1）使用与每个指令相关联的程序命令标签，（2）通过将浮点寄存器重命名表的有效位向量与其程序命令标签为所有检查点条目中最古老的程序订单标签与错误预测的分支或中断的指令的程序订单标签更年轻或更旧，以及（3）通过使用检查点条目的位置部分来替换寄存器的NEXT指针重命名表。

2. 发明授权

US5894419A System and method for robust clocking schemes for logic circuits 失效
标题翻译：用于逻辑电路的稳健时钟方案的系统和方法
公开(公告)号：US5894419A
公开(公告)日：1999-04-13
申请号：US845112
申请日：1997-04-21
申请人： Tiberiu Carol Galambos , Robert Paul Masleid , Israel Abraham Wagner
发明人： Tiberiu Carol Galambos , Robert Paul Masleid , Israel Abraham Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method according to the present invention for mapping a clocking scheme to determine robust clocking schemes in a logic circuit is disclosed. The circuit can be represented by a clocking graph, the clocking graph having at least one loop including a plurality of vertices, wherein two vertices represent each relevant signal, one for a rising edge and one for a falling edge. Additionally, a plurality of constraints of the logic circuit propagate through circuit delays. The method according to the present invention comprises the steps of selecting one of the vertices as a reference; assigning at least one of the plurality of vertices as an unknown; creating at least a first equation by setting the unknown as not equal to any of the other vertices for each constraint, the first equation being included in a set of equations; creating at least a second equation by setting a sum of times between edges equal to a number of phases in a cycle, the second equation representing the at least one loop in the clocking graph, wherein the second equation is also included in the set of equations; and solving the set of equations to provide a set of clocking schemes.
摘要翻译：公开了根据本发明的用于映射时钟方案以确定逻辑电路中的鲁棒时钟方案的系统和方法。电路可以由时钟图表示，时钟图具有包括多个顶点的至少一个循环，其中两个顶点表示每个相关信号，一个用于上升沿，一个用于下降沿。此外，逻辑电路的多个约束通过电路延迟传播。根据本发明的方法包括以下步骤：选择一个顶点作为参考; 将所述多个顶点中的至少一个分配为未知; 通过将未知数设置为不等于每个约束的任何其他顶点来创建至少第一等式，第一方程包括在一组方程中; 通过设置等于一个周期中的相数的边缘之间的时间之和来创建至少第二等式，第二方程表示时钟图中的至少一个循环，其中第二方程也包括在方程组中 ; 并求解该方程组以提供一组计时方案。

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