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1. 发明申请

US20090045677A1 Power control circuitry and method 有权
标题翻译：电源控制电路和方法
公开(公告)号：US20090045677A1
公开(公告)日：2009-02-19
申请号：US11889456
申请日：2007-08-13
申请人： Christophe Frey , Andrew John Sowden
发明人： Christophe Frey , Andrew John Sowden
IPC分类号： H02J1/00
CPC分类号： H03K19/0016 , H03K17/28 , H03K17/30 , Y10T307/461 , Y10T307/937 , Y10T307/951 , Y10T307/957
摘要： A power control circuitry and method of operation are provided for controlling the connection of a voltage source to an associated circuit when that circuit is to enter an active state of operation. The associated circuit has a plurality of circuit portions, and each circuit portion has at least one voltage line for connection to the voltage source. The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal. Each power switching circuit is responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level. Such an approach provides a simple and effective mechanism for reducing inrush current in a manner which is independent of process variations.
摘要翻译：提供功率控制电路和操作方法，用于在该电路进入活动状态时控制电压源与相关电路的连接。相关联的电路具有多个电路部分，并且每个电路部分具有用于连接到电压源的至少一个电压线。功率控制电路包括一系列功率开关电路，每个功率开关电路与电路部分中的一个相关联并且具有使能信号。每个功率开关电路响应于其使能信号被设置为将电压源连接到相关电路部分的至少一个电压线。此外，提供至少一个使能限定电路，每个这样的使能限定电路与功率切换电路中的一个相关联，并且被布置成产生用于确定提供给该系列中的稍后电力开关电路的使能信号的输出信号。当提供给相关联的功率开关电路的使能信号都被置位并且与该功率开关电路相关联的电路部分的至少一个电压线已经达到预定电压电平时，每个使能限定电路设置其输出信号。这种方法提供了一种简单而有效的机制，以独立于工艺变化的方式降低浪涌电流。

2. 发明授权

US07696649B2 Power control circuitry and method 有权
标题翻译：电源控制电路和方法
公开(公告)号：US07696649B2
公开(公告)日：2010-04-13
申请号：US11889456
申请日：2007-08-13
申请人： Christophe Frey , Andrew John Sowden
发明人： Christophe Frey , Andrew John Sowden
IPC分类号： H01H7/00 , H01H9/54
CPC分类号： H03K19/0016 , H03K17/28 , H03K17/30 , Y10T307/461 , Y10T307/937 , Y10T307/951 , Y10T307/957
摘要： The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.
摘要翻译：所述功率控制电路包括一系列功率开关电路，每个功率开关电路与所述电路部分中的一个相关联并且被提供有使能信号，并响应于其使能信号被设置为将所述电压源连接到所述至少一个电压相关电路部分的线。此外，提供至少一个使能限定电路，每个这样的使能限定电路与功率切换电路中的一个相关联，并且被布置成产生用于确定提供给该系列中的稍后电力开关电路的使能信号的输出信号。当提供给相关联的功率开关电路的使能信号都被置位并且与该功率开关电路相关联的电路部分的至少一个电压线已经达到预定电压电平时，每个使能限定电路设置其输出信号。

3. 发明申请

US20080297063A1 Power gating of circuits 失效
标题翻译：电路门电
公开(公告)号：US20080297063A1
公开(公告)日：2008-12-04
申请号：US11806258
申请日：2007-05-30
申请人： David John Willingham , Andrew John Sowden
发明人： David John Willingham , Andrew John Sowden
IPC分类号： H05B41/36
CPC分类号： H03K19/0016 , H03K17/164 , Y10T307/696
摘要： A control device for controlling power supplied to circuitry is disclosed. The circuitry comprises a plurality of portions, each of said plurality of circuit portions being arranged between a first voltage level source and a second voltage level source, said first and second voltage level sources being adapted to output different voltage levels; said control device being adapted to control power supplied to each of said plurality of circuit portions. The control device comprises: a plurality of power switching devices corresponding to said plurality of circuit portions, each power switching device being arranged between said first voltage level source and a corresponding circuit portion such that when one of said plurality of power switching devices is switched on a voltage level close to a voltage level output by said first voltage level source is supplied to said corresponding circuit portion and said corresponding circuit portion is powered up and when switched off said corresponding circuit portion is isolated from said first voltage level source and said corresponding circuit portion is powered down, said control device further comprising: at least one voltage equalisation switching device arranged between two power switching devices to provide a low resistance path between said two power switching devices when they are both turned on and to isolate said two power switching devices from each other when either are turned off.
摘要翻译：公开了一种用于控制提供给电路的功率的控制装置。所述电路包括多个部分，所述多个电路部分中的每一个被布置在第一电压电平源和第二电压电平源之间，所述第一和第二电压电平源适于输出不同的电压电平; 所述控制装置适于控制提供给所述多个电路部分中的每一个的电力。所述控制装置包括：对应于所述多个电路部分的多个功率开关装置，每个功率开关装置布置在所述第一电压电平源和对应的电路部分之间，使得当所述多个电力开关装置中的一个被接通时接近所述第一电压电平源输出的电压电平的电压电平被提供给所述对应的电路部分，并且所述对应的电路部分被加电，并且当所述相应的电路部分被断开时，所述对应的电路部分与所述第一电压电平源和所述相应的电路所述控制装置还包括：至少一个电压均衡切换装置，其布置在两个功率开关装置之间，以在所述两个功率开关装置都接通时提供低电阻路径，并且隔离所述两个功率开关装置当两者都关闭时，彼此相交。

4. 发明申请

US20100195365A1 ROM array 有权
标题翻译： ROM阵列
公开(公告)号：US20100195365A1
公开(公告)日：2010-08-05
申请号：US12320667
申请日：2009-01-30
申请人： Sriram Thyagarajan , Gus Yeung , Andrew John Sowden
发明人： Sriram Thyagarajan , Gus Yeung , Andrew John Sowden
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C7/14 , G11C7/22 , G11C2207/2281
摘要： A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.
摘要翻译：提供了一种ROM阵列，其包括多列存储器单元，其中每列存储器单元耦合到由该列存储器单元和相邻列的存储器单元共享的共享位线。每列存储器单元具有其自己的相关联的参考线，其被选择性地耦合到参考电位。当对存储器单元的相关联的列的存储器单元执行读取操作时，每个参考线耦合到参考电位。当对相邻列的存储器单元的存储单元执行读取操作时，每个参考线与参考电位分离。当共享位线在读取操作之前被预充电时，通过它们的存储器单元列相关联到共享位线的两个参考线与参考电位分离。因此，本发明提供了一种ROM阵列，其中产生泄漏减少和速度增加的优点，同时提供高密度设计。

5. 发明授权

US07558104B2 Power saving in memory arrays 有权
标题翻译：内存阵列省电
公开(公告)号：US07558104B2
公开(公告)日：2009-07-07
申请号：US11702200
申请日：2007-02-05
申请人： Andrew John Sowden , David Anthony New , Paul Darren Hoxey , Simon Christopher Reynolds
发明人： Andrew John Sowden , David Anthony New , Paul Darren Hoxey , Simon Christopher Reynolds
IPC分类号： G11C11/00
CPC分类号： G06F1/3203 , G06F1/3275 , G11C11/412 , Y02D10/14
摘要： An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.
摘要翻译：一组存储元件，每个存储元件包括数据输入和输出以及反馈回路，基本上所有的所述反馈回路形成为具有不对称性，使得在没有接收到输入数据信号时上电时，优先将值存储在所述反馈回路中，基本上所有的所述存储元件将优先输出相同的值。

6. 发明申请

US20080189483A1 Power saving in memory arrays 有权
标题翻译：内存阵列省电
公开(公告)号：US20080189483A1
公开(公告)日：2008-08-07
申请号：US11702200
申请日：2007-02-05
申请人： Andrew John Sowden , David Anthony New , Paul Darren Hoxey , Simon Christopher Reynolds
发明人： Andrew John Sowden , David Anthony New , Paul Darren Hoxey , Simon Christopher Reynolds
IPC分类号： G06F12/00
CPC分类号： G06F1/3203 , G06F1/3275 , G11C11/412 , Y02D10/14
摘要： An array of storage elements each comprising a data input and output and a feedback loop, substantially all of said feedback loops being formed with an asymmetry such that on power up when no input data signal is received a value is preferentially stored in said feedback loops such that substantially all of said storage elements will preferentially output a same value.
摘要翻译：一组存储元件，每个存储元件包括数据输入和输出以及反馈回路，基本上所有的所述反馈回路形成为具有不对称性，使得在没有接收到输入数据信号时上电时，优先将值存储在所述反馈回路中，基本上所有的所述存储元件将优先输出相同的值。

7. 发明授权

US07940546B2 ROM array 有权
标题翻译： ROM阵列
公开(公告)号：US07940546B2
公开(公告)日：2011-05-10
申请号：US12320667
申请日：2009-01-30
申请人： Sriram Thyagarajan , Gus Yeung , Andrew John Sowden
发明人： Sriram Thyagarajan , Gus Yeung , Andrew John Sowden
IPC分类号： G11C17/00
CPC分类号： G11C7/18 , G11C7/12 , G11C7/14 , G11C7/22 , G11C2207/2281
摘要： A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.
摘要翻译：提供了一种ROM阵列，其包括多列存储器单元，其中每列存储器单元耦合到由该列存储器单元和相邻列的存储器单元共享的共享位线。每列存储器单元具有其自己的相关联的参考线，其被选择性地耦合到参考电位。当对存储器单元的相关联的列的存储器单元执行读取操作时，每个参考线耦合到参考电位。当对相邻列的存储器单元的存储单元执行读取操作时，每个参考线与参考电位分离。当共享位线在读取操作之前被预充电时，通过它们的存储器单元列相关联到共享位线的两个参考线与参考电位分离。因此，本发明提供了一种ROM阵列，其中产生泄漏减少和速度增加的优点，同时提供高密度设计。

8. 发明授权

US07723867B2 Power gating of circuits 失效
标题翻译：电路门电
公开(公告)号：US07723867B2
公开(公告)日：2010-05-25
申请号：US11806258
申请日：2007-05-30
申请人： David John Willingham , Andrew John Sowden
发明人： David John Willingham , Andrew John Sowden
IPC分类号： H02J1/00 , H02J3/00
CPC分类号： H03K19/0016 , H03K17/164 , Y10T307/696
摘要： A control device for controlling power supplied to circuitry is disclosed. The circuitry comprises a plurality of portions, each of said plurality of circuit portions being arranged between a first voltage level source and a second voltage level source, said first and second voltage level sources being adapted to output different voltage levels; said control device being adapted to control power supplied to each of said plurality of circuit portions. The control device comprises: a plurality of power switching devices corresponding to said plurality of circuit portions, each power switching device being arranged between said first voltage level source and a corresponding circuit portion such that when one of said plurality of power switching devices is switched on a voltage level close to a voltage level output by said first voltage level source is supplied to said corresponding circuit portion and said corresponding circuit portion is powered up and when switched off said corresponding circuit portion is isolated from said first voltage level source and said corresponding circuit portion is powered down, said control device further comprising: at least one voltage equalization switching device arranged between two power switching devices to provide a low resistance path between said two power switching devices when they are both turned on and to isolate said two power switching devices from each other when either are turned off.
摘要翻译：公开了一种用于控制提供给电路的功率的控制装置。所述电路包括多个部分，所述多个电路部分中的每一个被布置在第一电压电平源和第二电压电平源之间，所述第一和第二电压电平源适于输出不同的电压电平; 所述控制装置适于控制提供给所述多个电路部分中的每一个的电力。所述控制装置包括：对应于所述多个电路部分的多个功率开关装置，每个功率开关装置布置在所述第一电压电平源和对应的电路部分之间，使得当所述多个电力开关装置中的一个被接通时接近所述第一电压电平源输出的电压电平的电压电平被提供给所述对应的电路部分，并且所述对应的电路部分被加电，并且当所述相应的电路部分被断开时，所述对应的电路部分与所述第一电压电平源和所述相应电路所述控制装置还包括：至少一个电压均衡切换装置，其布置在两个功率开关装置之间，以在所述两个功率开关装置都接通时提供低电阻路径，并且隔离所述两个功率开关装置当两者都关闭时，彼此相交。

9. 发明授权

US07005889B2 Level shifting in a data processing apparatus 有权
标题翻译：数据处理装置中的电平移位
公开(公告)号：US07005889B2
公开(公告)日：2006-02-28
申请号：US10887356
申请日：2004-07-09
申请人： Andrew John Sowden , Dipesh Ishwerbhai Patel , Nicholas Andrew Salter , Harry Edward Oldham
发明人： Andrew John Sowden , Dipesh Ishwerbhai Patel , Nicholas Andrew Salter , Harry Edward Oldham
IPC分类号： H03K19/0175
CPC分类号： G06F1/3203 , G06F1/3296 , H03K19/0185 , Y02D10/172
摘要： A data processing apparatus and method are provided for controlling level shifting. The data processing apparatus comprises a first component provided within a first voltage domain and operable to receive a first supply voltage, and a second component provided within a second voltage domain and operable to receive a second supply voltage. At least one of the first and second supply voltages are dynamically variable. The data processing apparatus further comprises an interface cell between the first and second voltage domains which is operable to receive a signal issued by the first component in the first voltage domain and destined for the second component. The interface cell comprises level shifting logic operable to convert the signal issued by the first component into a corresponding signal to be propagated to the second component in the second voltage domain. Further, bypass logic is provided which is operable in the event that the first supply voltage and second supply voltage are at the same voltage level to enable a bypass path around the level shifting logic such that the signal issued by the first component is propagated via the bypass path as the corresponding signal to the second component in the second voltage domain.
摘要翻译：提供了一种用于控制电平转换的数据处理装置和方法。数据处理装置包括设置在第一电压域内并可操作以接收第一电源电压的第一组件和设置在第二电压域内并可操作以接收第二电源电压的第二组件。第一和第二电源电压中的至少一个是动态可变的。数据处理装置还包括在第一和第二电压域之间的接口单元，其可操作以接收由第一电压域中的第一组件发出并发往第二组件的信号。接口单元包括电平移位逻辑，可操作以将由第一分量发出的信号转换为在第二电压域中传播到第二分量的对应信号。此外，提供了旁路逻辑，其可在第一电源电压和第二电源电压处于相同电压电平的情况下操作，以实现电平移位逻辑周围的旁路，使得由第一组件发出的信号经由旁路路径作为与第二电压域中的第二分量相对应的信号。

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