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    • 8. 发明授权
    • Multi-stage numeric counter oscillator
    • 多级数字计数振荡器
    • US07064616B2
    • 2006-06-20
    • US10748488
    • 2003-12-29
    • Peter Reichert
    • Peter Reichert
    • H03L7/00
    • G06F1/0328
    • A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.
    • 公开了一种数字计数器振荡器,其包括商累加器和余数累加器。 商累加器具有用于接收QUOTIENT值的可编程输入,参考时钟输入和多位输出。 该输出适于发送表示累积商数的输出值OUT。 响应于每个参考时钟周期,多位输出增加预定量。 剩余累加器包括可编程输入,用于接收相应的REMAINDER和DIVISOR值,参考时钟输入和表示累积的数字余数和小于预定数字整数的多位输出。 剩余累加器还包括具有用于接收编程除数值的第一输入的比较器和用于接收余数累加器多位输出的第二输入。 当余数多位输出达到预定义的整数值时,比较器可操作以产生用于应用于商积累器的递增进位信号。
    • 9. 发明授权
    • Pattern generator for a packet-based memory tester
    • 用于基于分组的内存测试器的模式生成器
    • US06389525B1
    • 2002-05-14
    • US09227690
    • 1999-01-08
    • Peter ReichertBill SopkinChris Reed
    • Peter ReichertBill SopkinChris Reed
    • G06F1200
    • G11C29/56G01R31/31813G01R31/31926
    • A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.
    • 公开了一种用于存储器测试器中的模式发生器,用于将分组地址和数据信号提供给基于分组的未被测试的存储器。 图案生成器包括用于生成外部分组存储器地址信号的地址源。 外部分组存储器地址信号表示被测存储器中的多个可寻址存储器元件。 多个数据发生器并行布置并耦合到地址源的输出端以接收分组存储器地址信号的至少一部分。 每个数据发生器具有逻辑可操作以从分组地址导出内部地址。 内部地址对应于被测存储器内的单独存储元件。 定序器设置在数据发生器的输出处,以便将数据发生器输出以分组波形分布以供应用于待测存储器。