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1. 发明授权

US06590657B1 Semiconductor structures and manufacturing methods 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US06590657B1
公开(公告)日：2003-07-08
申请号：US09408246
申请日：1999-09-29
申请人： Christian Summerer , Shahid Butt , Gerhard Kunkel , Uwe Paul Schroeder
发明人： Christian Summerer , Shahid Butt , Gerhard Kunkel , Uwe Paul Schroeder
IPC分类号： G01B1100
CPC分类号： G03F9/7076 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor body having an alignment mark comprising a material adapted to absorb impinging light and to radiate light in response to the absorption of the impinging light, such radiated light being radiated with a wavelength different from the wavelength of the impinging light. Also a method and apparatus for detecting an alignment mark on a semiconductor body. The method and apparatus successively scan an alignment illumination comprising the impinging light over the surface of the semiconductor surface and over the alignment mark. The impinging energy is reflected by the surface of the semiconductor when such impinging light is over and is reflected by the surface of the semiconductor. The impinging energy is absorbed by the material and is then radiated by the material when such impinging energy is scanned over such material. The reflected light is selectively filtered while the radiated light is passed to a detector.
摘要翻译：一种具有对准标记的半导体本体，包括适于吸收入射光并响应于入射光的吸收而辐射光的材料，这种辐射光以不同于入射光的波长的波长辐射。还有一种用于检测半导体本体上的对准标记的方法和装置。该方法和装置连续地扫描包括在半导体表面的表面上和对准标记上的入射光的对准照明。当这种入射光结束并被半导体的表面反射时，入射能量被半导体的表面反射。冲击能量被材料吸收，然后当这种冲击能量在这种材料上扫描时被材料辐射。当辐射光通过检测器时，反射光被选择性地过滤。

2. 发明授权

US06316168B1 Top layer imaging lithography for semiconductor processing 有权
标题翻译：用于半导体处理的顶层成像光刻技术
公开(公告)号：US06316168B1
公开(公告)日：2001-11-13
申请号：US09290319
申请日：1999-04-12
申请人： Shahid Butt , Uwe Paul Schroeder
发明人： Shahid Butt , Uwe Paul Schroeder
IPC分类号： G03F736
CPC分类号： H01L21/0276 , H01L21/31144 , Y10S430/151
摘要： A method for etching a surface includes the steps of providing an under layer formed on the surface and a top layer formed on the under layer. The top layer is patterned to expose portions of the under layer, and a layer including silicon is formed on the exposed portions of the under layer. The top layer is removed to expose the under layer in portions other than the portions of the under layer having the silicon layer thereon, and the under layer is etched in portions other than the portions of the under layer having the silicon layer thereon to expose the surface.
摘要翻译：一种用于蚀刻表面的方法包括以下步骤：提供形成在表面上的底层和形成在下层上的顶层。将顶层图案化以暴露下层的部分，并且在底层的暴露部分上形成包括硅的层。除去顶层以在除了其上具有硅层的下层的部分之外的部分中露出下层，并且在除了在其上具有硅层的下层的部分之外的部分中蚀刻下层以暴露表面。

3. 发明授权

US07074529B2 Phase-shift mask 失效
标题翻译：相移掩模
公开(公告)号：US07074529B2
公开(公告)日：2006-07-11
申请号：US10787118
申请日：2004-02-27
申请人： Shahid Butt , Gerhard Kunkel
发明人： Shahid Butt , Gerhard Kunkel
IPC分类号： G01F9/00
CPC分类号： G03F1/32 , G03F1/26 , G03F7/70325
摘要： The relative surface area sizes of portions having distinct phase-shift and transmission of light of a pattern on a phase-shift mask substantially obey the condition that the product of surface area and transmission of the electrical field strength is the same for all of the portions. Then, frequency doubling occurs due to vanishing zero order diffraction orders and in the case of high-transition attenuated phase-shift masks a large first order diffraction amplitude reveals an even an improved as compared with conventional phase-shift masks. Two-dimensional matrix-like structures particularly on attenuated or halftone phase-shift masks can be arranged to image high-density patterns on a semiconductor wafer. The duty cycles of pattern matrices can be chosen being different from one in two orthogonal directions nevertheless leading to frequency doubling.
摘要翻译：在相移掩模上具有明显的相移和图案的光的透射的部分的相对表面积大小基本上遵循对于所有部分的表面积和电场强度透射率的乘积相同的条件。然后，由于零阶衍射级消失而发生倍频，并且在高转变衰减相移掩模的情况下，与常规相移掩模相比，大的一级衍射幅度显示出均匀的改善。特别是在衰减或半色调相移掩模上的二维矩阵状结构可以被布置成对半导体晶片上的高密度图案进行成像。可以选择模式矩阵的占空比不同于两个正交方向上的一个，但是导致倍频。

4. 发明授权

US06842222B2 Method of reducing pitch on semiconductor wafer 失效
标题翻译：降低半导体晶片间距的方法
公开(公告)号：US06842222B2
公开(公告)日：2005-01-11
申请号：US10406888
申请日：2003-04-04
申请人： Gerhard Kunkel , Shahid Butt , Alan Thomas , Juergen Preuninger
发明人： Gerhard Kunkel , Shahid Butt , Alan Thomas , Juergen Preuninger
IPC分类号： G03B27/32 , G03B27/42 , G03B27/52 , G03F7/20 , G03F7/207
CPC分类号： G03F7/70141 , G03F7/70333
摘要： A projected image is formed during a material substrate. A photolithographic mask is illuminated with substantially coherent light at an oblique angle of incidence with respect to a surface of the photolithographic mask. The photolithographic mask includes a substantially transparent mask substrate and one or more lines and spaces patterns formed on the mask substrate and having a periodicity P. The mask substrate includes at least one phase shifting region. At least part of the light that is transmitted through the photolithographic mask is collected using one or more projection lenses which project the portion of the transmitted light onto the material substrate. The material substrate is disposed substantially parallel with, but at a distance from, a focal plane of the projection lens system. The phase shifting region of the mask substrate and the distance from the focal plane are selected such that a substantially focused image is projected onto the material substrate that includes the lines and spaces patterned but with a periodicity P/2.
摘要翻译：在材料基板期间形成投影图像。以相对于光刻掩模的表面的倾斜入射角的基本上相干的光照射光刻掩模。光刻掩模包括基本上透明的掩模基板和形成在掩模基板上并且具有周期P的一个或多个线和间隔图案。掩模基板包括至少一个相移区域。通过光刻掩模透射的光的至少一部分使用一个或多个将透射光的一部分投射到材料基底上的投影透镜来收集。材料基板设置成与投影透镜系统的焦平面大致平行，但距离投影透镜系统的焦平面。选择掩模基板的相移区域和与焦平面的距离，使得将基本上聚焦的图像投影到包括图案化但具有周期性P / 2的线和间隔的材料基板上。

5. 发明授权

US06606151B2 Grating patterns and method for determination of azimuthal and radial aberration 有权
标题翻译：用于确定方位角和径向像差的光栅图案和方法
公开(公告)号：US06606151B2
公开(公告)日：2003-08-12
申请号：US09916917
申请日：2001-07-27
申请人： Gerhard Kunkel , Shahid Butt , Joseph Kirk
发明人： Gerhard Kunkel , Shahid Butt , Joseph Kirk
IPC分类号： G01B900
CPC分类号： G01M11/0242
摘要： Methods and reticles for evaluating lenses are disclosed. In one instance, a reticle which permits light to pass therethrough is provided which includes a first surface with a grating profile formed thereon. The grating profile includes a plurality of grouped stepped portions. Each group of the stepped portions includes a first step which prevents light from propagating therethrough, a second step which propagates light therethrough and a third step which propagates light therethrough at an angle 60 degrees out of phase with the light propagated through the second step.
摘要翻译：公开了用于评估透镜的方法和掩模版。在一种情况下，提供允许光通过的掩模版，其包括形成有光栅轮廓的第一表面。光栅轮廓包括多个分组的阶梯部分。每组台阶部分包括防止光从其中传播的第一步骤，传播光的第二步骤，以及第三步骤，其以与第二步骤传播的光成60度角异相传播光。

6. 发明授权

US06566219B2 Method of forming a self aligned trench in a semiconductor using a patterned sacrificial layer for defining the trench opening 有权
标题翻译：使用图案化牺牲层在半导体中形成自对准沟槽以限定沟槽开口的方法
公开(公告)号：US06566219B2
公开(公告)日：2003-05-20
申请号：US09957937
申请日：2001-09-21
申请人： Gerhard Kunkel , Shahid Butt , Ramachandra Divakaruni , Armin M. Reith , Munir D. Naeem
发明人： Gerhard Kunkel , Shahid Butt , Ramachandra Divakaruni , Armin M. Reith , Munir D. Naeem
IPC分类号： H01L21475
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10891
摘要： A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) is formed over a semiconductor region (e.g., a silicon substrate). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench can be etched in the semiconductor region. The trench would be substantially aligned to the second material.
摘要翻译：形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。在一个方面，在半导体区域（例如，硅衬底）上形成第一材料（例如，多晶硅）的第一层。图案化第一层以去除第一材料的部分。然后可以沉积第二材料（例如，氧化物）以填充去除第一材料的部分。在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽。沟槽将基本上对准第二材料。

7. 发明授权

US06282116B1 Dynamic random access memory 失效
标题翻译：动态随机存取存储器
公开(公告)号：US06282116B1
公开(公告)日：2001-08-28
申请号：US09603337
申请日：2000-06-26
申请人： Gerhard Kunkel , Shahid Butt , Carl J Radens
发明人： Gerhard Kunkel , Shahid Butt , Carl J Radens
IPC分类号： G11C1124
CPC分类号： H01L27/10882 , G11C11/4097 , H01L27/10841
摘要： A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.
摘要翻译：动态随机存取存储器形成在芯片阵列中的硅芯片中，四个单元中的每一个在单个活动区域中。每个有源区域在两个十字准线的四端处具有垂直沟槽十字形。两个交叉点相交的有源区域的中心区域用作簇的四个晶体管的公共基极区域。基极区域的顶部用作四个晶体管的公共漏极，并且每个晶体管沿其相关联的垂直沟槽的壁具有提供其存储电容器的单独沟道。每个集群包括一个公共位线和四个单独的字线触点。

8. 发明授权

US06118683A Dynamic random access memory cell layout 有权
标题翻译：动态随机存取存储单元布局
公开(公告)号：US06118683A
公开(公告)日：2000-09-12
申请号：US407437
申请日：1999-09-29
申请人： Gerhard Kunkel , Shahid Butt , Carl J. Radens
发明人： Gerhard Kunkel , Shahid Butt , Carl J. Radens
IPC分类号： G11C11/4097 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： H01L27/10891 , G11C11/4097 , H01L27/10841
摘要： A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.
摘要翻译：动态随机存取存储器形成在芯片阵列中的硅芯片中，四个单元中的每一个在单个活动区域中。每个有源区域在两个十字准线的四端处具有垂直沟槽十字形。两个交叉点相交的有源区域的中心区域用作簇的四个晶体管的公共基极区域。基极区域的顶部用作四个晶体管的公共漏极，并且每个晶体管沿其相关联的垂直沟槽的壁具有提供其存储电容器的单独沟道。每个集群包括一个公共位线和四个单独的字线触点。

9. 发明申请

US20070041003A1 Focus blur measurement and control method 失效
标题翻译：聚焦模糊测量和控制方法
公开(公告)号：US20070041003A1
公开(公告)日：2007-02-22
申请号：US11206326
申请日：2005-08-18
申请人： Christopher Ausschnitt , Timothy Brunner , Shahid Butt , Daniel Corliss
发明人： Christopher Ausschnitt , Timothy Brunner , Shahid Butt , Daniel Corliss
IPC分类号： G03B27/52
CPC分类号： G03F7/70641 , G03F7/70533 , G03F7/70625
摘要： A method for optimizing imaging and process parameter settings in a lithographic pattern imaging and processing system. The method includes correlating the dimensions of a first set of at least one control pattern printed in a lithographic resist layer, measured at three or more locations on or within the pattern which correspond to differing dose, defocus and blur sensitivity. The method then includes measuring the dimensions on subsequent sets of control patterns, printed in a lithographic resist layer, at three or more locations on or within each pattern, of which a minimum of three locations match those measured in the first set, and determining the effective dose, defocus and blur values associated with forming the subsequent sets of control patterns by comparing the dimensions at the matching locations with the correlated dependencies.
摘要翻译：一种用于优化光刻图案成像和处理系统中的成像和工艺参数设置的方法。该方法包括将印刷在光刻抗蚀剂层中的至少一个控制图案的第一组的尺寸相关联，在对应于不同剂量，散焦和模糊灵敏度的图案之上或之内的三个或更多个位置处测量。该方法然后包括测量印刷在光刻抗蚀剂层中的随后的一组控制图案上的尺寸，位于每个图案上或每个图案上的三个或更多个位置，其中最少三个位置与在第一组中测量的位置匹配，并且确定通过将匹配位置处的尺寸与相关依赖关系进行比较来形成随后的控制模式组相关联的有效剂量，散焦和模糊值。

10. 发明申请

US20050009312A1 GATE LENGTH PROXIMITY CORRECTED DEVICE 审中-公开
标题翻译：门锁长度接近正确的设备
公开(公告)号：US20050009312A1
公开(公告)日：2005-01-13
申请号：US10604112
申请日：2003-06-26
申请人： Shahid Butt , Wayne Ellis , John Gabric
发明人： Shahid Butt , Wayne Ellis , John Gabric
IPC分类号： H01L29/423 , G06F17/50 , H01L21/3205 , H01L21/82 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L23/52 , H01L27/02 , H01L27/04 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/49 , H01L29/76
CPC分类号： H01L21/823437 , G06F17/5068 , H01L27/0207 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An electronic device including: a semiconductor substrate having an array of gate conductors, each having a length and a width, comprised of dummy gate conductors and functional gate conductors extending in a widthwise direction, the gate conductors positioned substantially parallel to each other in the widthwise direction and periodically spaced apart a fixed distance in a direction substantially perpendicular to the widthwise direction.
摘要翻译：一种电子设备，包括：半导体衬底，其具有各自具有长度和宽度的栅极导体阵列，所述栅极导体阵列包括虚拟栅极导体和沿宽度方向延伸的功能栅极导体，所述栅极导体在宽度方向上基本上彼此平行并且在基本上垂直于宽度方向的方向上周期性地间隔开固定距离。

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