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1. 发明授权

US09006801B2 Method for forming metal semiconductor alloys in contact holes and trenches 有权
标题翻译：在接触孔和沟槽中形成金属半导体合金的方法
公开(公告)号：US09006801B2
公开(公告)日：2015-04-14
申请号：US13013081
申请日：2011-01-25
申请人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L21/285 , H01L21/336 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/311 , H01L21/768
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.
摘要翻译：提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

2. 发明授权

US08614106B2 Liner-free tungsten contact 失效
标题翻译：无衬里钨触点
公开(公告)号：US08614106B2
公开(公告)日：2013-12-24
申请号：US13299573
申请日：2011-11-18
申请人： Christian Lavoie , Ahmet S. Ozcan , Filippos Papadatos
发明人： Christian Lavoie , Ahmet S. Ozcan , Filippos Papadatos
IPC分类号： H01L23/48
CPC分类号： H01L23/53261 , H01L21/28518 , H01L21/28556 , H01L21/76814 , H01L21/76876 , H01L21/76877 , H01L23/485 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.
摘要翻译：在具有富钨表面的镍 - 硅化钨上形成无衬里的钨接触。使用含钨无氟前体形成含钨层。含钨层可以用作后续成核层或成核层的胶层。钨塞通过标准工艺形成。结果是具有低电阻率的无衬里钨接触。

3. 发明授权

US07993987B1 Surface cleaning using sacrificial getter layer 有权
标题翻译：表面清洗采用牺牲吸气层
公开(公告)号：US07993987B1
公开(公告)日：2011-08-09
申请号：US12904346
申请日：2010-10-14
申请人： Randolph F. Knarr , Christian Lavoie , Ahmet S. Ozcan , Filippos Papadatos
发明人： Randolph F. Knarr , Christian Lavoie , Ahmet S. Ozcan , Filippos Papadatos
IPC分类号： H01L21/28
CPC分类号： H01L21/3221 , H01L21/0206 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method includes providing a substrate including a non-insulative, silicon-including region for silicidation, the substrate including one or more contaminants at a top surface thereof. A getter layer is deposited over the non-insulative, silicon-including region, the getter layer reacting with at least one of the one or more contaminants in the non-insulative, silicon-including region at approximately room temperature. The getter layer is removed, and siliciding of the non-insulative, silicon-including region is performed.
摘要翻译：一种方法包括提供包括用于硅化的非绝缘的含硅区域的衬底，所述衬底在其顶表面上包括一种或多种污染物。吸气剂层沉积在非绝缘的含硅区域上，吸气剂层在大约室温下与非绝缘的含硅区域中的一种或多种污染物中的至少一种反应。除去吸气剂层，进行非绝缘性含硅区域的硅化。

4. 发明申请

US20130127058A1 LINER-FREE TUNGSTEN CONTACT 失效
标题翻译：无线触摸屏
公开(公告)号：US20130127058A1
公开(公告)日：2013-05-23
申请号：US13299573
申请日：2011-11-18
申请人： Christian Lavoie , Ahmet S. Ozcan , Filippos Papadatos
发明人： Christian Lavoie , Ahmet S. Ozcan , Filippos Papadatos
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/53261 , H01L21/28518 , H01L21/28556 , H01L21/76814 , H01L21/76876 , H01L21/76877 , H01L23/485 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A liner-less tungsten contact is formed on a nickel-tungsten silicide with a tungsten rich surface. A tungsten-containing layer is formed using tungsten-containing fluorine-free precursors. The tungsten-containing layer may act as a glue layer for a subsequent nucleation layer or as the nucleation layer. The tungsten plug is formed by standard processes. The result is a liner-less tungsten contact with low resistivity.
摘要翻译：在具有富钨表面的镍 - 硅化钨上形成无衬里的钨接触。使用含钨无氟前体形成含钨层。含钨层可以用作后续成核层或成核层的胶层。钨塞通过标准工艺形成。结果是具有低电阻率的无衬里钨接触。

5. 发明申请

US20120187460A1 METHOD FOR FORMING METAL SEMICONDUCTOR ALLOYS IN CONTACT HOLES AND TRENCHES 有权
标题翻译：金属半导体合金在接触孔和高岭土中的形成方法
公开(公告)号：US20120187460A1
公开(公告)日：2012-07-26
申请号：US13013081
申请日：2011-01-25
申请人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
发明人： Christian Lavoie , Zhengwen Li , Ahmet S. Ozcan , Filippos Papadatos , Chengwen Pei , Jian Yu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/28518 , H01L21/31116 , H01L21/32053 , H01L21/321 , H01L21/32133 , H01L21/76802 , H01L21/76805 , H01L21/76829 , H01L23/535 , H01L29/1054 , H01L29/45 , H01L29/456 , H01L29/458 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7843 , H01L29/7845 , H01L29/7849
摘要： A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.
摘要翻译：提供一种形成半导体器件的方法，包括在半导体容纳表面上形成第一金属半导体合金，在第一金属半导体合金上形成电介质层，在电介质层中形成开口以提供第一金属半导体合金，并且在第一金属半导体合金的暴露表面上形成第二金属半导体合金。在另一个实施例中，该方法包括在半导体衬底的沟道区上形成栅极结构，在至少源极区和漏极区上形成电介质层，在电介质层中形成开口以提供暴露表面，半导体衬底在所述半导体衬底的暴露表面上形成第一金属半导体合金，并在所述第一金属半导体合金上形成第二金属半导体合金。

6. 发明申请

US20140073130A1 FORMING NICKEL-PLATINUM ALLOY SELF-ALIGNED SILICIDE CONTACTS 有权
标题翻译：形成镍 - 铂合金自对准硅化物接触
公开(公告)号：US20140073130A1
公开(公告)日：2014-03-13
申请号：US13613579
申请日：2012-09-13
申请人： David F. Hilscher , Christian Lavoie , Ahmet S. Ozcan
发明人： David F. Hilscher , Christian Lavoie , Ahmet S. Ozcan
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： A method of performing a silicide contact process comprises a forming a nickel-platinum alloy (NiPt) layer over a semiconductor device structure; performing a first rapid thermal anneal (RTA) so as to react portions of the NiPt layer in contact with semiconductor regions of the semiconductor device structure, thereby forming metal rich silicide regions; performing a first wet etch to remove at least a nickel constituent of unreacted portions of the NiPt layer; performing a second wet etch using a dilute Aqua Regia treatment comprising nitric acid (HNO3), hydrochloric acid (HCl) and water (H2O) to remove any residual platinum material from the unreacted portions of the NiPt layer; and following the dilute Aqua Regia treatment, performing a second RTA to form final silicide contact regions from the metal rich silicide regions.
摘要翻译：执行硅化物接触工艺的方法包括在半导体器件结构上形成镍 - 铂合金（NiPt）层; 执行第一快速热退火（RTA），以使NiPt层的与半导体器件结构的半导体区域接触的部分反应，由此形成富金属硅化物区域; 执行第一湿蚀刻以去除至少NiPt层的未反应部分的镍组分; 使用包含硝酸（HNO 3），盐酸（HCl）和水（H 2 O）的稀释Aqua Regia处理进行第二次湿蚀刻以从NiPt层的未反应部分去除任何残余的铂材料; 并且在稀释的Aqua Regia处理之后，执行第二个RTA从富金属硅化物区形成最终的硅化物接触区。

7. 发明授权

US08652963B2 MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture 有权
标题翻译：具有均匀薄的硅化物层的MOSFET集成电路及其制造方法
公开(公告)号：US08652963B2
公开(公告)日：2014-02-18
申请号：US13237732
申请日：2011-09-20
申请人： Bin Yang , Christian Lavoie , Emre Alptekin , Ahmet S. Ozcan , Cung D. Tran , Mark Raymond
发明人： Bin Yang , Christian Lavoie , Emre Alptekin , Ahmet S. Ozcan , Cung D. Tran , Mark Raymond
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/6659 , H01L29/7833
摘要： An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
摘要翻译：提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。在金属/硅界面处形成均匀薄的无定形混合合金层时，除去过量的（未反应的）金属。该器件被退火以促进在衬底表面上形成薄的硅化物层，其在宽和窄接触沟槽的底部显示均匀的厚度。

8. 发明授权

US08456011B2 Method to control metal semiconductor micro-structure 有权
公开(公告)号：US08456011B2
公开(公告)日：2013-06-04
申请号：US13006664
申请日：2011-01-14
申请人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
发明人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
IPC分类号： H01L23/532
CPC分类号： H01L21/768 , H01L21/28518 , H01L23/485 , H01L29/456 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

9. 发明授权

US08278200B2 Metal-semiconductor intermixed regions 有权
标题翻译：金属半导体混合区域
公开(公告)号：US08278200B2
公开(公告)日：2012-10-02
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

10. 发明申请

US20110062525A1 METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR 有权
标题翻译：不同硅酸盐的方法和结构以及被提高或提高的源/排水以改善场效应晶体管
公开(公告)号：US20110062525A1
公开(公告)日：2011-03-17
申请号：US12560585
申请日：2009-09-16
申请人： Christian Lavoie , Viorel C. Ontalus , Ahmet S. Ozcan
发明人： Christian Lavoie , Viorel C. Ontalus , Ahmet S. Ozcan
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/28 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/7848
摘要： A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc.
摘要翻译：一种方法形成集成电路结构。该方法在第一类场效应晶体管上形成保护层，并从第二种场效应晶体管上方去除应力衬垫。然后，该方法从第二类型场效应晶体管的源极区和漏极区去除第一类型的硅化物层，但是将第一类型硅化物层的至少一部分留在第二类型场效应晶体管的栅极导体上。该方法在栅极导体和第二类场效应晶体管的源极和漏极区域上形成第二类型的硅化物层。所形成的第二类硅化物层与第一型硅化物层不同。例如，第一型硅化物层和第二类型硅化物层可以包括不同的材料，不同的厚度，不同的晶体取向和/或不同的化学相等。

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