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1. 发明申请

US20050053124A1 System and method for implementing a delta-sigma modulator integrity supervisor 有权
标题翻译：用于实现delta-Σ调制器完整性主管的系统和方法
公开(公告)号：US20050053124A1
公开(公告)日：2005-03-10
申请号：US10786670
申请日：2004-02-25
申请人： Christian Eichrodt , Frode Larsen , Arnold Muralt
发明人： Christian Eichrodt , Frode Larsen , Arnold Muralt
IPC分类号： H04L7/00 , H04L27/00 , H04B17/00
CPC分类号： H04L25/0266 , H04L7/0008 , H04L7/0079 , H04L27/0002
摘要： A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level. The clock detector may comprise a pair of monostable circuits, an inverter, and a NAND gate and may be configured to reset the transmitter if a “missing” clock signal state is detected. The present invention can also be viewed as providing a method for preventing a transmission unit from forwarding signals that may result in a DC flow condition. In its broadest terms, the method can be described as: monitoring a data signal; generating a first output signal in response to a data signal having an anomalous condition; monitoring a clock signal; and generating a second output signal in response to clock signal having an anomalous condition.
摘要翻译：一种用于构建信号完整性监督器的系统和方法，当传输路径信号指示潜在的损坏的发射机操作模式时，能够检测和触发适当的响应。本发明的系统和方法利用了Delta-Sigma调制器（DSM）的固有特性，这使得在标称操作期间遇到长串连续或零的概率非常小。信号完整性监控器通过监视数字和数模转换器的时钟输入来确保安全的发射机操作。系统可以包括数据信号监视器和时钟信号监视器。数据监视器可以包括比较器和计数器，并且可以被配置为在检测到具有连续电压电平的数据流时对线路驱动器断电。时钟检测器可以包括一对单稳态电路，反相器和NAND门，并且可以被配置为如果检测到“丢失”的时钟信号状态则复位发射机。本发明还可以被视为提供一种防止传输单元转发可能导致DC流动状态的信号的方法。在最广泛的术语中，该方法可以被描述为：监视数据信号; 响应于具有异常状态的数据信号产生第一输出信号; 监视时钟信号; 以及响应于具有异常状态的时钟信号产生第二输出信号。

2. 发明授权

US07558316B2 System and method for implementing a delta-sigma modulator integrity supervisor 有权
公开(公告)号：US07558316B2
公开(公告)日：2009-07-07
申请号：US10786670
申请日：2004-02-25
申请人： Christian Eichrodt , Frode Larsen , Arnold Muralt
发明人： Christian Eichrodt , Frode Larsen , Arnold Muralt
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L25/0266 , H04L7/0008 , H04L7/0079 , H04L27/0002
摘要： A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level. The clock detector may comprise a pair of monostable circuits, an inverter, and a NAND gate and may be configured to reset the transmitter if a “missing” clock signal state is detected. The present invention can also be viewed as providing a method for preventing a transmission unit from forwarding signals that may result in a DC flow condition. In its broadest terms, the method can be described as: monitoring a data signal; generating a first output signal in response to a data signal having an anomalous condition; monitoring a clock signal; and generating a second output signal in response to clock signal having an anomalous condition.

3. 发明授权

US07555036B2 System and method for implementing a delta-sigma modulator integrity supervisor 有权
标题翻译：用于实现delta-Σ调制器完整性主管的系统和方法
公开(公告)号：US07555036B2
公开(公告)日：2009-06-30
申请号：US10786669
申请日：2004-02-25
申请人： Christian Eichrodt , Frode Larsen , Arnold Muralt
发明人： Christian Eichrodt , Frode Larsen , Arnold Muralt
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L25/0266 , H04L7/0008 , H04L7/0079 , H04L27/0002
摘要： A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level. The clock detector may comprise a pair of monostable circuits, an inverter, and a NAND gate and may be configured to reset the transmitter if a “missing” clock signal state is detected. The present invention can also be viewed as providing a method for preventing a transmission unit from forwarding signals that may result in a DC flow condition. In its broadest terms, the method can be described as: monitoring a data signal; generating a first output signal in response to a data signal having an anomalous condition; monitoring a clock signal; and generating a second output signal in response to clock signal having an anomalous condition.
摘要翻译：一种用于构建信号完整性监督器的系统和方法，当传输路径信号指示潜在的损坏的发射机操作模式时，能够检测和触发适当的响应。本发明的系统和方法利用了Delta-Sigma调制器（DSM）的固有特性，这使得在标称操作期间遇到长串连续或零的概率非常小。信号完整性监控器通过监视数字和数模转换器的时钟输入来确保安全的发射机操作。系统可以包括数据信号监视器和时钟信号监视器。数据监视器可以包括比较器和计数器，并且可以被配置为在检测到具有连续电压电平的数据流时对线路驱动器断电。时钟检测器可以包括一对单稳态电路，反相器和NAND门，并且可以被配置为如果检测到“丢失”的时钟信号状态则复位发射机。本发明还可以被视为提供一种防止传输单元转发可能导致DC流动状态的信号的方法。在最广泛的术语中，该方法可以被描述为：监视数据信号; 响应于具有异常状态的数据信号产生第一输出信号; 监视时钟信号; 以及响应于具有异常状态的时钟信号产生第二输出信号。

4. 发明授权

US06765954B1 System and method for implementing a delta-sigma modulator integrity supervisor 有权
标题翻译：用于实现delta-Σ调制器完整性主管的系统和方法
公开(公告)号：US06765954B1
公开(公告)日：2004-07-20
申请号：US09640123
申请日：2000-08-16
申请人： Christian Eichrodt , Frode Larsen , Arnold Muralt
发明人： Christian Eichrodt , Frode Larsen , Arnold Muralt
IPC分类号： H04B138
CPC分类号： H04L25/0266 , H04L7/0008 , H04L7/0079 , H04L27/0002
摘要： A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level. The clock detector may comprise a pair of monostable circuits, an inverter, and a NAND gate and may be configured to reset the transmitter if a “missing” clock signal state is detected. The present invention can also be viewed as providing a method for preventing a transmission unit from forwarding signals that may result in a DC flow condition. In its broadest terms, the method can be described as: monitoring a data signal; generating a first output signal in response to a data signal having an anomalous condition; monitoring a clock signal; and generating a second output signal in response to clock signal having an anomalous condition.
摘要翻译：一种用于构建信号完整性监督器的系统和方法，当传输路径信号指示潜在的损坏的发射机操作模式时，能够检测和触发适当的响应。本发明的系统和方法利用了Delta-Sigma调制器（DSM）的固有特性，这使得在标称操作期间遇到长串连续或零的概率非常小。信号完整性监控器通过监视数字和数模转换器的时钟输入来确保安全的发射机操作。系统可以包括数据信号监视器和时钟信号监视器。数据监视器可以包括比较器和计数器，并且可以被配置为在检测到具有连续电压电平的数据流时对线路驱动器断电。时钟检测器可以包括一对单稳态电路，反相器和NAND门，并且可以被配置为如果检测到“丢失”的时钟信号状态则复位发射机。本发明还可以被视为提供一种防止传输单元转发可能导致DC流动状态的信号的方法。在最广泛的术语中，该方法可以被描述为：监视数据信号; 响应于具有异常状态的数据信号产生第一输出信号; 监视时钟信号; 以及响应于具有异常状态的时钟信号产生第二输出信号。

5. 发明授权

US07031378B1 Unified DSL transceiver 失效
标题翻译：统一DSL收发器
公开(公告)号：US07031378B1
公开(公告)日：2006-04-18
申请号：US09888735
申请日：2001-06-25
申请人： Arnold Muralt , Christian Eichrodt
发明人： Arnold Muralt , Christian Eichrodt
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L25/0264
摘要： A single unified digital subscriber line (DSL) transceiver can be used for DSL applications, can be integrated on a single board or chip, or within a less board space. An embodiment of the unified DSL transceiver comprises a transmit circuit coupled to a line driver/transformer circuit. The line driver/transformer circuit is coupled to a receive circuit that comprises a switching circuit. A signal is transmitted from the transmit circuit to the line driver/transformer circuit; the switching circuit is configured based on DSL applications, and the signal is propagated from the line driver/transformer circuit to a line.
摘要翻译：单个统一数字用户线（DSL）收发器可用于DSL应用，可集成在单个板或芯片上，或集成在较少的电路板空间内。统一DSL收发器的实施例包括耦合到线路驱动器/变压器电路的发送电路。线路驱动器/变压器电路耦合到包括开关电路的接收电路。信号从发送电路发送到线路驱动器/变压器电路; 开关电路基于DSL应用来配置，并且信号从线路驱动器/变压器电路传播到线路。

6. 发明授权

US07061987B1 Wide-band analog front-end for DSL applications 失效
标题翻译：用于DSL应用的宽带模拟前端
公开(公告)号：US07061987B1
公开(公告)日：2006-06-13
申请号：US10214341
申请日：2002-08-06
申请人： Nianxiong Tan , Francis M. Caster, II , Christian Eichrodt , Brian Borrong Horng , James J. Zhao
发明人： Nianxiong Tan , Francis M. Caster, II , Christian Eichrodt , Brian Borrong Horng , James J. Zhao
IPC分类号： H04K1/10
CPC分类号： H04L5/14 , H04L5/023 , H04M11/062 , H04Q2213/13034 , H04Q2213/13039 , H04Q2213/1319
摘要： An analog front-end circuit and method that supports multiple digital subscriber line (DSL) standards, including asymmetric digital subscriber line (ADSL) and very-high speed digital subscriber line (VDSL) is disclosed. The circuit incorporates multiple circuit blocks that can be selectively included into the transmit and receive paths of a DSL signal. It also permits selectable gain settings for signal amplifiers, and frequency bandwidth for signal filters that may be included in the transmit and receive paths. The receive path includes an analog-to-digital converter (ADC) that operates close to and exceeds the Nyquist sampling rate.
摘要翻译：公开了一种支持多种数字用户线（DSL）标准的模拟前端电路和方法，包括非对称数字用户线（ADSL）和超高速数字用户线（VDSL）。该电路结合了可以选择性地包括在DSL信号的发送和接收路径中的多个电路块。它还允许信号放大器的可选增益设置和可能包含在发送和接收路径中的信号滤波器的频率带宽。接收路径包括操作接近并超过奈奎斯特采样速率的模拟 - 数字转换器（ADC）。

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