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1. 发明授权

US07493576B2 CDM ESD event protection in application circuits 失效
标题翻译：应用电路中的CDM ESD事件保护
公开(公告)号：US07493576B2
公开(公告)日：2009-02-17
申请号：US11349356
申请日：2006-02-07
申请人： William Loh , Li Lynn Ooi , Choshu Ito
发明人： William Loh , Li Lynn Ooi , Choshu Ito
IPC分类号： G06F17/50 , G06F9/00
CPC分类号： G06F17/5036
摘要： Methods and structure for improved design remediation for previously inexplicable damage to core circuits of an application circuit design caused by CDM ESD events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Features and aspects hereof automatically alter an application circuit design to provide remediation by various techniques to reduce the magnitude of such inductive coupling and to thereby reduce susceptibility of the application circuit to damage from CDM ESD events. The modifications may be enforced as rules during initial design of the application circuit or as reconfiguration of a design in response to simulation to discover inappropriate coupling in the design.
摘要翻译：改进设计修复的方法和结构，以前由于CDM ESD事件引起的应用电路设计的核心电路的莫名其妙的损害。本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。其特征和方面自动改变应用电路设计，以通过各种技术提供补救以减少这种电感耦合的幅度，从而降低应用电路对CDM ESD事件的损害的敏感性。在应用电路的初始设计期间，修改可以被执行为规则，或者作为响应于模拟的设计的重新配置以发现设计中的不适当的耦合。

2. 发明授权

US07458044B2 CDM ESD event simulation and remediation thereof in application circuits 失效
标题翻译： CDM ESD事件模拟及其在应用电路中的修复
公开(公告)号：US07458044B2
公开(公告)日：2008-11-25
申请号：US11349358
申请日：2006-02-07
申请人： Choshu Ito , Li Lynn Ooi , William Loh
发明人： Choshu Ito , Li Lynn Ooi , William Loh
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5036
摘要： Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such previously inexplicable damage to core circuits of an application circuit design is caused by inductive coupling between the non-core circuits and the core circuits of an application circuit design. Improved simulation techniques in accordance with features and aspects hereof may predict where such inductive coupling may cause damage to core circuits. Other features and aspects hereof may alter an application circuit design to provide remediation by automated insertion of additional buffer circuitry to core traces of the core circuitry that may be impacted by such inductive coupling.
摘要翻译：改进CDM ESD事件仿真和修复电路设计的方法和结构，以纠正由此类事件引起的应用电路设计对核心电路的以前不可思议的损害。本发明的特征和方面注意到，对应用电路设计的核心电路的这种以前的莫名其妙的损害是由非核心电路和应用电路设计的核心电路之间的电感耦合引起的。根据其特征和方面的改进的仿真技术可以预测这种感应耦合可能会对核心电路造成损害。本发明的其它特征和方面可以改变应用电路设计，以通过将附加的缓冲电路自动插入到可能受这种电感耦合影响的核心电路的芯线迹来提供补救。

3. 发明申请

US20100194616A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 有权
标题翻译：用于同步，重定时模数转换的系统和方法
公开(公告)号：US20100194616A1
公开(公告)日：2010-08-05
申请号：US12669481
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个，子级交错。在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和第四子电平交错同步到第一时钟相位。

4. 发明申请

US20090296292A1 Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure 有权
标题翻译：采用微机电系统（MEMS）结构的静电放电保护电路
公开(公告)号：US20090296292A1
公开(公告)日：2009-12-03
申请号：US12128108
申请日：2008-05-28
申请人： Tze Wee Chen , William Loh , Choshu Ito
发明人： Tze Wee Chen , William Loh , Choshu Ito
IPC分类号： H02H9/00 , H01H59/00
CPC分类号： H01H59/0009 , H02H9/046
摘要： An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.
摘要翻译：用于保护耦合到信号垫的主机电路与在信号焊盘处发生的ESD事件的ESD保护电路包括至少一个电连接到信号焊盘的MEMS开关。 MEMS开关包括适于连接到信号焊盘的第一接触结构和适于连接到电压源的第二接触结构。在ESD事件期间，第一和第二接触结构耦合在一起，用于将ESD电流从信号焊盘分流到电压源。在没有ESD事件的情况下，第一和第二接触结构彼此电隔离。第一和第二接触结构中的至少一个包括用于减小第一和第二接触结构之间的接触粘附的钝化层。

5. 发明授权

US08798981B2 Circuit simulation using step response analysis in the frequency domain 有权
标题翻译：电路仿真使用频域中的阶跃响应分析
公开(公告)号：US08798981B2
公开(公告)日：2014-08-05
申请号：US12143895
申请日：2008-06-23
申请人： Choshu Ito , William Loh
发明人： Choshu Ito , William Loh
IPC分类号： G06G7/56 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5009 , G06F17/5045
摘要： A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.
摘要翻译：用于模拟电路对应用于电路的ESD输入激励的响应的方法包括以下步骤：将电路的描述接收到电路仿真程序中，该电路包括指示在该电路中的磁耦合的至少一个互感元件电路在非线性元件的各个DC偏置点处产生电路中的非线性元件的线性近似; 获得电路的频域传递函数; 获得电路的时域脉冲响应作为频域传递函数的函数; 积分时域脉冲响应以产生电路的阶跃响应，阶跃响应指示电路对ESD输入刺激的响应; 以及分析电路的阶跃响应以确定电路是否将在对应于电路的规定参数内运行。

6. 发明申请

US20100100859A1 DESIGN METHODOLOGY FOR PREVENTING FUNCTIONAL FAILURE CAUSED BY CDM ESD 有权
标题翻译：防止CDM ESD导致功能失效的设计方法
公开(公告)号：US20100100859A1
公开(公告)日：2010-04-22
申请号：US12255002
申请日：2008-10-21
申请人： Choshu Ito , Tze Wee Chen , William Loh
发明人： Choshu Ito , Tze Wee Chen , William Loh
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5036 , G06F2217/72 , G06F2217/82
摘要： A design methodology which prevents functional failure caused by CDM ESD events. A transistor model is used to model the final states of cells, and a simulator is then used to identify invulnerable cells. Cells that are potential failure sites are then identified. The cells which have been identified as being potential victims are replaced by the previously-identified invulnerable cells that have the identical logic function. On the other hand, if a cell with identical function cannot be found, an invulnerable buffer cell (that will not effect logic function) can be inserted in front of the potential victim transistor as protection. By replacing all the potential victim cells with cells which have been determined to be invulnerable, the resulting design will be guaranteed to be CDM ESD tolerant.
摘要翻译：一种防止CDM ESD事件引起功能故障的设计方法。晶体管模型用于对细胞的最终状态建模，然后使用模拟器来识别不可侵入的细胞。然后鉴定潜在的故障部位的细胞。被识别为潜在受害者的细胞由具有相同逻辑功能的先前识别的无形细胞所取代。另一方面，如果不能发现具有相同功能的单元，则可以在潜在的牺牲晶体管的前面插入不可变缓冲单元（不会影响逻辑功能）作为保护。通过用已被确定为无害的细胞代替所有潜在的受害细胞，所得到的设计将被保证是CDM耐受性的。

7. 发明申请

US20070019345A1 Circuit protection system 有权
标题翻译：电路保护系统
公开(公告)号：US20070019345A1
公开(公告)日：2007-01-25
申请号：US11174135
申请日：2005-06-30
申请人： William Loh , Ken Doniger , Payman Zarkesh-Ha , Jau-Wen Chen , Choshu Ito
发明人： William Loh , Ken Doniger , Payman Zarkesh-Ha , Jau-Wen Chen , Choshu Ito
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： A system and method for protecting a circuit. The system includes a protection circuit that includes an inverter and a capacitor coupled to the inverter. The inverter and the capacitor are implemented using logic circuits of a circuit core, and the inverter shunts electrostatic discharge ESD current through the capacitor. According to the system and method disclosed herein, because the protection circuit shunt circuit shunts ESD current using logic circuits of the circuit core, ESD protection is achieved while not requiring large FETs. Also, the protection circuit protects circuits against ESD events that conventional FET cannot protect.
摘要翻译：一种用于保护电路的系统和方法。该系统包括保护电路，该保护电路包括逆变器和耦合到逆变器的电容器。逆变器和电容器使用电路核心的逻辑电路实现，并且逆变器分流通过电容器的静电放电ESD电流。根据本文公开的系统和方法，由于保护电路并联电路使用电路核心的逻辑电路来分流ESD电流，所以在不需要大的FET的情况下实现ESD保护。此外，保护电路保护电路免受常规FET无法保护的ESD事件。

8. 发明授权

US07956790B2 Systems and methods for synchronous, retimed analog to digital conversion 有权
标题翻译：用于同步，重新定时模数转换的系统和方法
公开(公告)号：US07956790B2
公开(公告)日：2011-06-07
申请号：US12669481
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H03M1/34
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个，子级交错。在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和第四子电平交错同步到第一时钟相位。

9. 发明授权

US07656340B2 Systems and methods for pipelined analog to digital conversion 有权
标题翻译：用于流水线模数转换的系统和方法
公开(公告)号：US07656340B2
公开(公告)日：2010-02-02
申请号：US12134523
申请日：2008-06-06
申请人： Sergey Gribok , Choshu Ito , William Loh , Erik Chmelar
发明人： Sergey Gribok , Choshu Ito , William Loh , Erik Chmelar
IPC分类号： H03M1/38
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a pipelined analog to digital converter is disclosed that includes two or more comparators. A first of the comparators is operable to compare an analog input to a first voltage reference upon assertion of the first clock, and a second of the comparators is operable to compare the analog input to a second voltage reference upon assertion of the second clock. The pipelined analog to digital converters further include a multiplexer tree with at least a first tier multiplexer and a second tier multiplexer. The first tier multiplexer receives an output of the first comparator and an output of the second comparator, and the second tier multiplexer receives an output derived from the first tier multiplexer. The second tier multiplexer provides an output bit. A bit enable set is used as a selector input to the first tier multiplexer and the second tier multiplexer, and the bit enable set includes one or more output bits from preceding bit periods.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种流水线模数转换器，其包括两个或更多个比较器。比较器中的第一个可操作以在断言第一时钟时将模拟输入与第一参考电压进行比较，并且第二比较器可用于在断言第二时钟时将模拟输入与第二参考电压进行比较。流水线模数转换器还包括具有至少第一层多路复用器和第二层多路复用器的复用器树。第一层多路复用器接收第一比较器的输出和第二比较器的输出，并且第二层多路复用器接收从第一层多路复用器导出的输出。第二层复用器提供输出位。位使能集合用作对第一层多路复用器和第二层多路复用器的选择器输入，并且位使能集包括来自先前位周期的一个或多个输出位。

10. 发明申请

US20090319251A1 Circuit Simulation Using Step Response Analysis in the Frequency Domain 有权
标题翻译：在频域中使用阶跃响应分析的电路仿真
公开(公告)号：US20090319251A1
公开(公告)日：2009-12-24
申请号：US12143895
申请日：2008-06-23
申请人： Choshu Ito , William Loh
发明人： Choshu Ito , William Loh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5009 , G06F17/5045
摘要： A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.
摘要翻译：用于模拟电路对应用于电路的ESD输入激励的响应的方法包括以下步骤：将电路的描述接收到电路仿真程序中，该电路包括指示在该电路中的磁耦合的至少一个互感元件电路在非线性元件的各个DC偏置点处产生电路中的非线性元件的线性近似; 获得电路的频域传递函数; 获得电路的时域脉冲响应作为频域传递函数的函数; 积分时域脉冲响应以产生电路的阶跃响应，阶跃响应指示电路对ESD输入刺激的响应; 以及分析电路的阶跃响应以确定电路是否将在对应于电路的规定参数内运行。

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