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1. 发明授权

US07064601B2 Reference voltage generating circuit using active resistance device 失效
公开(公告)号：US07064601B2
公开(公告)日：2006-06-20
申请号：US09955458
申请日：2001-09-18
申请人： Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
发明人： Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G05F1/46
CPC分类号： G05F3/262
摘要： A reference voltage generating circuit includes a current mirror circuit having first and second current paths formed between a first power source terminal and a second power source terminal in which the current mirror circuit is operated in response to a voltage level of the second current path, a reference voltage output node for providing a reference voltage and being located on the second current path, an active resistance device formed on the first current path to be operated in a linear region of a current-voltage characteristic curve of the active resistance device, and a voltage supply circuit for supplying the active resistance device with an enable voltage to control the active resistance device to be operated in the linear region.

2. 发明授权

US07463511B2 Phase change memory device using multiprogramming method 有权
标题翻译：相变存储器件采用多重编程方式
公开(公告)号：US07463511B2
公开(公告)日：2008-12-09
申请号：US11723361
申请日：2007-03-19
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。存储单元阵列包括多个块单元，每个块单元连接在相应的一对字线驱动器之间。写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流的内存块。

3. 发明申请

US20070242503A1 Phase change memory device using multiprogramming method 有权
标题翻译：相变存储器件采用多重编程方式
公开(公告)号：US20070242503A1
公开(公告)日：2007-10-18
申请号：US11723361
申请日：2007-03-19
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array comprises a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit comprises a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。存储单元阵列包括多个块单元，每个块单元连接在对应的一对字线驱动器之间。写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流的内存块。

4. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

5. 发明申请

US20060186483A1 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US20060186483A1
公开(公告)日：2006-08-24
申请号：US11324112
申请日：2005-12-30
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/76
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
摘要翻译：提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体之间的间隙区域多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

6. 发明申请

US20080303016A1 PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：使用单元的相变存储器件及其制造方法
公开(公告)号：US20080303016A1
公开(公告)日：2008-12-11
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L45/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
摘要翻译：提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体之间的间隙区域多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

7. 发明授权

US07427531B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07427531B2
公开(公告)日：2008-09-23
申请号：US11324112
申请日：2005-12-30
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L21/06
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
摘要翻译：提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体之间的间隙区域多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

8. 发明授权

US07317655B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07317655B2
公开(公告)日：2008-01-08
申请号：US11327967
申请日：2006-01-09
申请人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C8/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

9. 发明申请

US20060164896A1 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US20060164896A1
公开(公告)日：2006-07-27
申请号：US11327967
申请日：2006-01-09
申请人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Du-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：提供了一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件。半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多条第一线路中的相应第一线路，而存储器单元的第二端子连接到多个第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

10. 发明授权

US07796425B2 Control of set/reset pulse in response to peripheral temperature in PRAM device 有权
标题翻译：根据PRAM器件的外围温度控制置位/复位脉冲
公开(公告)号：US07796425B2
公开(公告)日：2010-09-14
申请号：US11985975
申请日：2007-11-19
申请人： Byung-Gil Choi , Choong-Keun Kwak , Woo-Yeong Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Woo-Yeong Cho
IPC分类号： G11C11/00 , G11C7/04 , G11C11/4193 , G11C11/4197
CPC分类号： G11C13/0069 , G11C7/04 , G11C7/1078 , G11C7/1096 , G11C13/0004 , G11C2013/0078
摘要： A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.
摘要翻译：用于PRAM（相变随机存取存储器）装置的驱动器电路包括响应于置位/复位脉冲而产生置位/复位电流的写入驱动器。此外，温度补偿器响应于PRAM器件的外围温度来控制置位/复位脉冲的脉冲宽度。例如，温度补偿器将脉冲宽度保持为基本恒定，而与外围温度无关。在另一个例子中，温度补偿器降低脉冲宽度，以提高外围温度。

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