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1. 发明授权

US06456114B1 Power conserving CMOS semiconductor integrated circuit 失效
标题翻译：省电CMOS半导体集成电路
公开(公告)号：US06456114B1
公开(公告)日：2002-09-24
申请号：US09861647
申请日：2001-05-22
申请人： Chizuru Inoshita , Kazuo Aoki , Toshinori Inoshita
发明人： Chizuru Inoshita , Kazuo Aoki , Toshinori Inoshita
IPC分类号： H03K19003
CPC分类号： H03K19/00323
摘要： A semiconductor integrated circuit device includes a control circuit for coping with time differences in signals propagating along by differences in routes of the circuit device. In a definite data interval when changes of all signals have been completed, the control circuit outputs a received signal. In an indefinite data interval when changes of all signals have not been completed, the control circuit outputs a fixed signal irrespective of signal level of a received signal. The control circuit thus prevents irregular signal changes caused by the time differences before definition of data to subsequent circuits.
摘要翻译：一种半导体集成电路器件，包括控制电路，用于应对沿着电路器件的路径差异传播的信号中的时间差。在完成所有信号的改变的确定的数据间隔中，控制电路输出接收的信号。在所有信号的改变尚未完成的无限数据间隔中，控制电路输出固定信号，而与接收信号的信号电平无关。因此，控制电路防止在将数据定义为后续电路之前的时间差引起的不规则信号变化。

2. 发明授权

US06724212B2 Method for testing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路测试方法
公开(公告)号：US06724212B2
公开(公告)日：2004-04-20
申请号：US10205313
申请日：2002-07-26
申请人： Chizuru Inoshita , Kazuo Aoki
发明人： Chizuru Inoshita , Kazuo Aoki
IPC分类号： G01R3126
CPC分类号： G01R31/3004
摘要： In a method of testing a semiconductor integrated circuit, an input signal is applied to the semiconductor integrated circuit. Current passing through the elements of the semiconductor integrated circuit is repeatedly measured while sequentially changing the logical state of the elements. The standard deviation of the currents measured is calculated and a semiconductor integrated circuit is determined to be defective if the standard deviation exceeds a threshold value.
摘要翻译：在半导体集成电路的测试方法中，向半导体集成电路施加输入信号。在依次改变元件的逻辑状态的同时重复地测量穿过半导体集成电路元件的电流。计算测量的电流的标准偏差，并且如果标准偏差超过阈值，则半导体集成电路被确定为有缺陷的。

3. 发明授权

US06563323B2 Method for testing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路测试方法
公开(公告)号：US06563323B2
公开(公告)日：2003-05-13
申请号：US10205312
申请日：2002-07-26
申请人： Chizuru Inoshita , Kazuo Aoki
发明人： Chizuru Inoshita , Kazuo Aoki
IPC分类号： G01R3128
CPC分类号： G01R31/3004
摘要： In a method of testing a semiconductor integrated circuit, an input signal is supplied to a logic circuit of the semiconductor integrated circuit. Current from a static power source passing through the semiconductor integrated circuit is repeatedly meansured while a logic state of the semiconductor integrated circuit is sequentially changed. Maximum and minimum currents are selected from the measured currents and an average current calculated from the measured currents. A determination is made that the semiconductor integrated circuit is defective when either of the difference between the average and maximum currents or the difference between the average and minimum currents exceeds a threshold value.
摘要翻译：在半导体集成电路的测试方法中，将输入信号提供给半导体集成电路的逻辑电路。当半导体集成电路的逻辑状态顺序地改变时，重复地使来自通过半导体集成电路的静态电源的电流。从测量的电流和从测量电流计算的平均电流中选择最大和最小电流。当平均和最大电流之间的差异或平均和最小电流之间的差异超过阈值时，确定半导体集成电路是有缺陷的。

4. 发明授权

US06674300B2 Method for testing a semiconductor integrated circuit when a difference between two consecutive current exceeds a threshold value 失效
标题翻译：当两个连续电流之间的差超过阈值时测试半导体集成电路的方法
公开(公告)号：US06674300B2
公开(公告)日：2004-01-06
申请号：US10205311
申请日：2002-07-26
申请人： Chizuru Inoshita , Kazuo Aoki
发明人： Chizuru Inoshita , Kazuo Aoki
IPC分类号： G01R3128
CPC分类号： G01R31/3004
摘要： In a method of testing a semiconductor integrated circuit, setting of a logical state of elements that constitute a semiconductor integrated circuit to be measured is sequentially changed. The current from a static-time power source current passing through the elements is measured several times while the settings are changed. Any two consecutive currents are obtained. When the difference between the two consecutive current exceeds a threshold value it is determined that the semiconductor integrated circuit is defective.
摘要翻译：在半导体集成电路的测试方法中，依次改变构成要测量的半导体集成电路的元件的逻辑状态的设定。通过元件的静态电源电流的电流在设定改变时进行多次测量。获得任何两个连续的电流。当两个连续电流之间的差超过阈值时，确定半导体集成电路有缺陷。

5. 发明授权

US06477115B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06477115B1
公开(公告)日：2002-11-05
申请号：US09627452
申请日：2000-07-27
申请人： Chizuru Inoshita , Kazuo Aoki
发明人： Chizuru Inoshita , Kazuo Aoki
IPC分类号： G04F1000
CPC分类号： G01R31/2882 , G01R31/3016
摘要： In a semiconductor integrated circuit, a monitor circuit for evaluation is provided on a semiconductor substrate in an input/output buffer circuit region. This monitor circuit includes a delay circuit, a first flip-flop circuit on the input side of the delay circuit, and a second flip-flop circuit on the output side of the delay circuit.
摘要翻译：在半导体集成电路中，在输入/输出缓冲电路区域中的半导体衬底上提供用于评估的监视电路。该监视电路包括延迟电路，延迟电路输入侧的第一触发器电路和延迟电路的输出侧的第二触发电路。

6. 发明授权

US06446231B1 Method for testing a semiconductor integrated circuit when a difference between max current and min current exceeds a threshold value 失效
标题翻译：当最大电流和最小电流之间的差超过阈值时测试半导体集成电路的方法
公开(公告)号：US06446231B1
公开(公告)日：2002-09-03
申请号：US09496257
申请日：2000-02-01
申请人： Chizuru Inoshita , Kazuo Aoki
发明人： Chizuru Inoshita , Kazuo Aoki
IPC分类号： G01R3128
CPC分类号： G01R31/3004
摘要： In a method of testing a semiconductor integrated circuit, setting of a logical state of elements that constitute a semiconductor integrated circuit to be measured is sequentially changed. The current from a static-time power source current passing through the elements is measured several times while the settings are changed. Maximum and minimum currents are obtained. When the difference between the maximum and the minimum current exceeds a threshold value it is determined that the semiconductor integrated circuit is defective.
摘要翻译：在半导体集成电路的测试方法中，依次改变构成要测量的半导体集成电路的元件的逻辑状态的设定。通过元件的静态电源电流的电流在设定改变时进行多次测量。获得最大和最小电流。当最大和最小电流之间的差超过阈值时，确定半导体集成电路有缺陷。

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