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1. 发明授权

US07888704B2 Semiconductor device for electrostatic discharge protection 有权
标题翻译：用于静电放电保护的半导体器件
公开(公告)号：US07888704B2
公开(公告)日：2011-02-15
申请号：US12222746
申请日：2008-08-15
申请人： Chiu-Chih Chiang , Han-Chung Tai
发明人： Chiu-Chih Chiang , Han-Chung Tai
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly.
摘要翻译：公开了一种用于静电放电保护的半导体器件，并且至少包括高压寄生器可控硅整流器（HVSCR）和二极管。 HVSCR具有阳极和阴极，HVSCR的阴极耦合到地面。串联连接到HVSCR的二极管也具有阳极和阴极。二极管的阳极耦合到HVSCR的阳极，二极管的阴极耦合到施加正电压的端子。二极管具有第二导电类型区域，其可以构造成形成彼此间隔开的几个条或小块。这些小块可以是任何形状，并定期或随机排列。

2. 发明申请

US20100038677A1 Semiconductor device for electrostatic discharge protection 有权
标题翻译：用于静电放电保护的半导体器件
公开(公告)号：US20100038677A1
公开(公告)日：2010-02-18
申请号：US12222746
申请日：2008-08-15
申请人： Chiu-Chih Chiang , Han-Chung Tai
发明人： Chiu-Chih Chiang , Han-Chung Tai
IPC分类号： H01L29/74
CPC分类号： H01L27/0262 , H01L29/7436
摘要： A semiconductor device for electrostatic discharge protection is disclosed, and at least comprises a high-voltage parasite silicon controlled rectifier (HVSCR) and a diode. The HVSCR has an anode and a cathode, and the cathode of HVSCR is coupled to a ground. The diode, coupled to the HVSCR in series, also has an anode and a cathode. The anode of the diode is coupled to the anode of the HVSCR, and the cathode of the diode is coupled to a terminal applied with a positive voltage. The diode has a second conductivity type zone that could be constructed to form several strips or small blocks spaced apart from each other. Those small blocks could be any shapes and arranged regularly or randomly.
摘要翻译：公开了一种用于静电放电保护的半导体器件，并且至少包括高压寄生器可控硅整流器（HVSCR）和二极管。 HVSCR具有阳极和阴极，并且HVSCR的阴极耦合到地面。串联连接到HVSCR的二极管也具有阳极和阴极。二极管的阳极耦合到HVSCR的阳极，二极管的阴极耦合到施加正电压的端子。二极管具有第二导电类型区域，其可以构造成形成彼此间隔开的几个条或小块。这些小块可以是任何形状，并定期或随机排列。

3. 发明授权

US08492801B2 Semiconductor structure with high breakdown voltage and resistance 有权
标题翻译：半导体结构具有高击穿电压和电阻
公开(公告)号：US08492801B2
公开(公告)日：2013-07-23
申请号：US11798206
申请日：2007-05-11
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/66
CPC分类号： H01L28/20
摘要： A semiconductor structure with high breakdown voltage and high resistance and method for manufacturing the same. The semiconductor structure at least comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; two first wells having the first conductive type and formed within the deep well; a second well having the first conductive type and formed between the two first wells within the deep well, and an implant dosage of the second well lighter than an implant dosage of each of the two first wells; and two first doping regions having the first conductive type and respectively formed within the two first wells.
摘要翻译：具有高击穿电压和高电阻的半导体结构及其制造方法。半导体结构至少包括具有第一导电类型的衬底; 在衬底中形成有第二导电类型的深阱; 具有第一导电类型并形成在深井内的两个第一阱; 具有第一导电类型并形成在深井内的两个第一阱之间的第二阱，以及比两个第一孔中的每一个的植入物剂量轻的第二阱的植入剂量; 和具有第一导电类型并分别形成在两个第一阱内的两个第一掺杂区域。

4. 发明申请

US20080036027A1 INTEGRATED CIRCUIT FOR A HIGH-SIDE TRANSISTOR DRIVER 有权
标题翻译：用于高侧晶体管驱动器的集成电路
公开(公告)号：US20080036027A1
公开(公告)日：2008-02-14
申请号：US11464075
申请日：2006-08-11
申请人： Chiu-Chih Chiang , Chih-Feng Huang , Ta-yung Yang
发明人： Chiu-Chih Chiang , Chih-Feng Huang , Ta-yung Yang
IPC分类号： H01L29/00
CPC分类号： H01L27/0629
摘要： The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well serve as the isolation structures. The low voltage control circuit is located outside the deep N well and the floating circuit is located inside the deep N well. The deep N well forms a high voltage junction barrier for isolating the control circuit from the floating circuit.
摘要翻译：公开了高压集成电路。高压集成电路包括低压控制电路，浮置电路，P衬底，设置在衬底中的深N阱以及设置在P衬底中的多个P阱。 P井和深N井作为隔离结构。低压控制电路位于深N阱外部，浮动电路位于深N阱内。深N阱形成用于将控制电路与浮置电路隔离的高压结屏障。

5. 发明申请

US20080001195A1 INTEGRATED CIRCUIT WITH HIGH VOLTAGE JUNCTION STRUCTURE 有权
标题翻译：具有高电压结构的集成电路
公开(公告)号：US20080001195A1
公开(公告)日：2008-01-03
申请号：US11426941
申请日：2006-06-28
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/94
CPC分类号： H01L27/092 , H01L21/823892
摘要： The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.
摘要翻译：高压集成电路包括P基板。在衬底中设置N阱势垒。形成P阱的分离的P扩散区域设置在基板中用作隔离结构。低压控制电路位于N阱屏障外。浮动电路位于N阱屏障内。为了在浮置电路和衬底之间形成高压结屏障，浮动电路的器件的最大空间受到限制。

6. 发明授权

US08125008B2 Schottky device and process of making the same comprising a geometry gap 有权
标题翻译：肖特基器件及其制造方法包括几何间隙
公开(公告)号：US08125008B2
公开(公告)日：2012-02-28
申请号：US11601131
申请日：2006-11-17
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/66
CPC分类号： H01L29/872 , H01L29/0692
摘要： A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.
摘要翻译：提供了一种肖特基器件及其制造方法。肖特基器件包括衬底，深阱，肖特基接触和欧姆接触。衬底掺杂有第一类型的离子。深阱掺杂有第二类离子，并形成在衬底中。肖特基接触器与深井接触第一电极。欧姆接触接触具有重掺杂区域的第二电极，第二种类型的离子在深阱中。其中深阱具有在肖特基接触下形成的宽度的几何间隙，第一类型的离子和第二类型的离子是互补的，并且间隙的宽度调节击穿电压。

7. 发明授权

US07732890B2 Integrated circuit with high voltage junction structure 有权
标题翻译：具有高压结结构的集成电路
公开(公告)号：US07732890B2
公开(公告)日：2010-06-08
申请号：US11426941
申请日：2006-06-28
申请人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
发明人： Chiu-Chih Chiang , Chih-Feng Huang , You-Kuo Wu , Long Shih Lin
IPC分类号： H01L29/00
CPC分类号： H01L27/092 , H01L21/823892
摘要： The high voltage integrated circuit comprises a P substrate. An N well barrier is disposed in the substrate. Separated P diffusion regions forming P wells are disposed in the substrate for serving as the isolation structures. The low voltage control circuit is located outside the N well barrier. A floating circuit is located inside the N well barrier. In order to develop a high voltage junction barrier in between the floating circuit and the substrate, the maximum space of devices of the floating circuit is restricted.
摘要翻译：高压集成电路包括P基片。在衬底中设置N阱势垒。形成P阱的分离的P扩散区域设置在基板中用作隔离结构。低压控制电路位于N阱屏障外。浮动电路位于N阱屏障内。为了在浮置电路和衬底之间形成高压结屏障，浮动电路的器件的最大空间受到限制。

8. 发明申请

US20080248638A1 PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR 有权
标题翻译：制造电压控制晶体管的过程
公开(公告)号：US20080248638A1
公开(公告)日：2008-10-09
申请号：US12132605
申请日：2008-06-03
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L21/22
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0878 , H01L29/0886 , H01L29/42368 , H01L29/861
摘要： The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential.
摘要翻译：本发明提供一种利用漏极端子和辅助区域之间的寄生电阻器的自驱动LDMOS。寄生电阻形成在准连接深N型阱中的两个耗尽边界之间。当两个耗尽边界夹闭时，栅极端子处的栅极电压电位在所述漏极端子处的漏极电压电位处被钳位。由于栅极电压电位被设计为等于或高于启动阈值电压，所以LDMOS被相应地导通。此外，不需要额外的管芯空间和掩模工艺来制造寄生电阻器。此外，本发明的寄生电阻器不降低LDMOS的击穿电压和操作速度。此外，当两个耗尽边界夹断时，栅极电压电位不随着漏极 - 电压电位的增加而变化。

9. 发明申请

US20080042241A1 Voltage-controlled semiconductor structure, resistor, and manufacturing processes thereof 有权
标题翻译：电压控制半导体结构，电阻及其制造方法
公开(公告)号：US20080042241A1
公开(公告)日：2008-02-21
申请号：US11507293
申请日：2006-08-21
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/8605 , H01L29/66166
摘要： Voltage-controlled semiconductor structures, voltage-controlled resistors, and manufacturing processes are provided. The semiconductor structure comprises a substrate, a first doped well, and a second doped well. The substrate is doped with a first type of ions. The first doped well is with a second type of ions and is formed in the substrate. The second doped well is with the second type of ions and is formed in the substrate. The first type of ions and the second type of ions are complementary. A resistor is formed between the first doped well and the second doped well. A resistivity of the resistor is controlled by a differential voltage. A resistivity of the resistor relates to a first depth of the first doped well, a second depth of the second doped well, and a distance between the first doped well and the second doped well. The resistivity of the resistor is higher than that of a well resistor formed in a single doped well with the second type of ions.
摘要翻译：提供了压控半导体结构，压控电阻器和制造工艺。半导体结构包括衬底，第一掺杂阱和第二掺杂阱。衬底掺杂有第一类型的离子。第一掺杂阱具有第二类离子，并形成在衬底中。第二掺杂阱是与第二类型的离子形成在衬底中。第一类离子和第二类离子是互补的。在第一掺杂阱和第二掺杂阱之间形成电阻器。电阻的电阻率由差分电压控制。电阻器的电阻率涉及第一掺杂阱的第一深度，第二掺杂阱的第二深度以及第一掺杂阱和第二掺杂阱之间的距离。电阻器的电阻率高于在具有第二类型离子的单个掺杂阱中形成的阱电阻器的电阻率。

10. 发明授权

US07759769B2 Semiconductor structure of a high side driver 有权
标题翻译：高边驱动器的半导体结构
公开(公告)号：US07759769B2
公开(公告)日：2010-07-20
申请号：US11489558
申请日：2006-07-20
申请人： Chiu-Chih Chiang , Chih-Feng Huang
发明人： Chiu-Chih Chiang , Chih-Feng Huang
IPC分类号： H01L29/06
CPC分类号： H01L23/62 , H01L21/765 , H01L24/48 , H01L27/0805 , H01L29/0847 , H01L29/7835 , H01L2224/48091 , H01L2924/00014 , H01L2924/19041 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor structure of a high side driver includes an ion-doped junction. The ion-doped junction includes a substrate and a deep well. The deep well is formed in the substrate and has a first concave structure. The ion-doped junction includes a semiconductor region connected to the first concave structure of the deep well and having substantially the same ion-doping concentration as the substrate.
摘要翻译：高侧驱动器的半导体结构包括离子掺杂结。离子掺杂结包括衬底和深阱。深孔形成在基板中并具有第一凹形结构。离子掺杂结包括连接到深阱的第一凹陷结构并且具有与衬底基本上相同的离子掺杂浓度的半导体区域。

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