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1. 发明授权

US08724420B2 SRAM write assist apparatus 有权
标题翻译： SRAM写入辅助装置
公开(公告)号：US08724420B2
公开(公告)日：2014-05-13
申请号：US13105382
申请日：2011-05-11
申请人： Chiting Cheng , Chung-Cheng Chou , Tsung-yung Jonathan Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Tsung-yung Jonathan Chang
IPC分类号： G11C11/413
CPC分类号： G11C11/419 , G11C11/41 , G11C29/021 , G11C29/023 , G11C29/028
摘要： An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.
摘要翻译： SRAM写入辅助装置包括定时器单元和分压器。分压器单元被配置为将电压电位分压到较低电平。在写入操作中，分压器的输出连接到存储单元。定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

2. 发明申请

US20120287736A1 SRAM Write Assist Apparatus 有权
标题翻译： SRAM写辅助装置
公开(公告)号：US20120287736A1
公开(公告)日：2012-11-15
申请号：US13105382
申请日：2011-05-11
申请人： Chiting Cheng , Chung-Cheng Chou , Tsung-yung Jonathan Chang
发明人： Chiting Cheng , Chung-Cheng Chou , Tsung-yung Jonathan Chang
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/021 , G11C29/023 , G11C29/028
摘要： An SRAM write assist apparatus comprises a timer unit and a voltage divider. The voltage divider unit is configured to divide a voltage potential down to a lower level. The output of the voltage divider is connected to a memory cell in a write operation. The timer unit is configured to generate a pulse having a width inversely proportional to the voltage potential applied to a memory chip. Furthermore, the timer unit controls the period in which a lower voltage from the output of the voltage divider is applied to the memory cell. Moreover, external level and timing programmable signals can be used to further adjust the voltage divider's ratio and the pulse width from the timer unit. By employing the SRAM write assist apparatus, a memory chip can perform a reliable and fast write operation.
摘要翻译： SRAM写入辅助装置包括定时器单元和分压器。分压器单元被配置为将电压电位分压到较低电平。在写入操作中，分压器的输出连接到存储单元。定时器单元被配置为产生具有与施加到存储芯片的电压电位成反比的宽度的脉冲。此外，定时器单元控制将来自分压器的输出的较低电压施加到存储单元的周期。此外，可以使用外部电平和定时可编程信号来进一步调整分压器的比例和来自定时器单元的脉冲宽度。通过采用SRAM写入辅助装置，存储器芯片可以执行可靠且快速的写入操作。

3. 发明授权

US08587992B2 Data-aware SRAM systems and methods forming same 有权
公开(公告)号：US08587992B2
公开(公告)日：2013-11-19
申请号：US13168581
申请日：2011-06-24
申请人： Chien-Yuan Chen , Yi-Tzu Chen , Hau-Tai Shieh , Tsung-yung Jonathan Chang
发明人： Chien-Yuan Chen , Yi-Tzu Chen , Hau-Tai Shieh , Tsung-yung Jonathan Chang
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C11/412 , G11C11/413
摘要： Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

4. 发明申请

US20120327705A1 Data-Aware SRAM Systems and Methods Forming Same 有权
标题翻译：数据感知SRAM系统和方法形成相同
公开(公告)号：US20120327705A1
公开(公告)日：2012-12-27
申请号：US13168581
申请日：2011-06-24
申请人： Chien-Yuan Chen , Yi-Tzu Chen , Hau-Tai Shieh , Tsung-yung Jonathan Chang
发明人： Chien-Yuan Chen , Yi-Tzu Chen , Hau-Tai Shieh , Tsung-yung Jonathan Chang
IPC分类号： G11C11/34 , G11C5/14 , G11C11/00
CPC分类号： G11C11/417 , G11C11/412 , G11C11/413
摘要： Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.
摘要翻译： SRAM单元的示例性实施例，用于SRAM系统的新的控制单元以及SRAM系统的实施例在此被描述。 SRAM单元被配置为接收具有与第一输入电压信号不同的值的第一输入电压信号和第二输入电压信号，并且保持第一存储值信号和第二存储值信号。控制电路被配置为接收第一输入电压信号和第二输入电压信号，并且由睡眠信号，选择信号和数据输入信号控制，使得控制电路的输出对数据是敏感的输入信号。 SRAM系统包括多个SRAM单元，控制所公开的控制电路，其中SRAM单元分别具有由数据输入信号及其补码信号控制的两个输入电压信号。

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