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    • 1. 发明授权
    • Liquid crystal display with crosstalk interference suppression based on gray-level variation of a frame to be displayed and related method
    • 液晶显示器具有串扰干扰抑制,基于要显示的帧的灰度变化和相关方法
    • US08878881B2
    • 2014-11-04
    • US13300667
    • 2011-11-21
    • Ching-Lin LiYi-Fan LinJen-Chieh Chen
    • Ching-Lin LiYi-Fan LinJen-Chieh Chen
    • G09G3/36
    • G09G3/36G09G3/3607G09G3/3655G09G3/3696G09G2320/0209G09G2320/0257
    • A liquid crystal display having common voltage compensation mechanism includes a liquid-crystal capacitor common electrode for receiving a liquid-crystal capacitor common voltage, a storage capacitor common electrode for receiving a storage capacitor common voltage, a common voltage generator for providing the liquid-crystal capacitor common voltage according to a preliminary common voltage, a common voltage compensation circuit electrically connected to the liquid-crystal capacitor common electrode and the storage capacitor common electrode, and a timing controller electrically connected to the common voltage compensation circuit. The common voltage compensation circuit is utilized for generating the storage capacitor common voltage through performing a ripple inverting operation according to the liquid-crystal capacitor common voltage, the preliminary common voltage and a compensation control signal. The timing controller is employed to analyze an image input signal for generating the compensation control signal.
    • 具有公共电压补偿机构的液晶显示器包括用于接收液晶电容器公共电压的液晶电容器公共电极,用于接收存储电容器公共电压的辅助电容器公共电极,用于提供液晶的公共电压发生器 根据初步公共电压的电容器公共电压,电连接到液晶电容器公共电极和辅助电容器公共电极的公共电压补偿电路,以及电连接到公共电压补偿电路的定时控制器。 公共电压补偿电路用于通过根据液晶电容器公共电压,初步公共电压和补偿控制信号执行纹波反转操作来产生存储电容器公共电压。 采用定时控制器来分析用于产生补偿控制信号的图像输入信号。
    • 2. 发明申请
    • LIQUID CRYSTAL DISPLAY HAVING COMMON-VOLTAGE COMPENSATION MECHANISM AND COMMON-VOLTAGE COMPENSATION METHOD
    • 具有普通电压补偿机构和通用电压补偿方法的液晶显示
    • US20120293560A1
    • 2012-11-22
    • US13300667
    • 2011-11-21
    • Ching-Lin LiYi-Fan LinJen-Chieh Chen
    • Ching-Lin LiYi-Fan LinJen-Chieh Chen
    • G09G5/10G09G5/00G09G3/36
    • G09G3/36G09G3/3607G09G3/3655G09G3/3696G09G2320/0209G09G2320/0257
    • A liquid crystal display having common voltage compensation mechanism includes a liquid-crystal capacitor common electrode for receiving a liquid-crystal capacitor common voltage, a storage capacitor common electrode for receiving a storage capacitor common voltage, a common voltage generator for providing the liquid-crystal capacitor common voltage according to a preliminary common voltage, a common voltage compensation circuit electrically connected to the liquid-crystal capacitor common electrode and the storage capacitor common electrode, and a timing controller electrically connected to the common voltage compensation circuit. The common voltage compensation circuit is utilized for generating the storage capacitor common voltage through performing a ripple inverting operation according to the liquid-crystal capacitor common voltage, the preliminary common voltage and a compensation control signal. The timing controller is employed to analyze an image input signal for generating the compensation control signal.
    • 具有公共电压补偿机构的液晶显示器包括用于接收液晶电容器公共电压的液晶电容器公共电极,用于接收存储电容器公共电压的辅助电容器公共电极,用于提供液晶的公共电压发生器 根据初步公共电压的电容器公共电压,电连接到液晶电容器公共电极和辅助电容器公共电极的公共电压补偿电路,以及电连接到公共电压补偿电路的定时控制器。 公共电压补偿电路用于通过根据液晶电容器公共电压,初步公共电压和补偿控制信号执行纹波反转操作来产生存储电容器公共电压。 采用定时控制器来分析用于产生补偿控制信号的图像输入信号。
    • 3. 发明授权
    • Source-driving circuit, display apparatus and operation method thereof
    • 源极驱动电路,显示装置及其操作方法
    • US08605067B2
    • 2013-12-10
    • US13308815
    • 2011-12-01
    • Jen-Chieh ChenChao-Ching HsuChing-Lin Li
    • Jen-Chieh ChenChao-Ching HsuChing-Lin Li
    • G06F3/038G09G5/00
    • G09G3/3614G09G3/3688G09G2310/0224G09G2310/0248G09G2310/0275G09G2310/0297G09G2330/023
    • A source-driving circuit comprises a plurality of first and second data-outputting units, a first and a second charge-sharing units and a charge-sharing switch circuit. The first and second data-outputting units have corresponding first and second output terminals respectively for outputting data signals with a first polarity and a second polarity. The first and second charge-sharing units comprise a plurality of first and second switches respectively. Each first switch is electrically connected between each two first output terminals and each two second output terminals. Each second switch is electrically connected between one of the first outputting terminals and a corresponding one of the second outputting terminals. A charge-sharing switch circuit is electrically connected to the first and second charge-sharing units for outputting a switch signal to the first and second charge-sharing units according to a polarity signal, so as to determine the on/off statuses of the first and second switches.
    • 源极驱动电路包括多个第一和第二数据输出单元,第一和第二电荷共享单元和电荷共享开关电路。 第一和第二数据输出单元分别具有相应的第一和第二输出端,用于输出具有第一极性和第二极性的数据信号。 第一和第二电荷共享单元分别包括多个第一和第二开关。 每个第一开关电连接在每两个第一输出端子和每两个第二输出端子之间。 每个第二开关电连接在第一输出端子之一和第二输出端子中的相应一个之间。 电荷共享开关电路电连接到第一和第二电荷共享单元,用于根据极性信号将开关信号输出到第一和第二电荷共享单元,以便确定第一和第二电荷共享单元的开/关状态 和第二开关。
    • 8. 发明申请
    • COMPUTER SYSTEM AND POWER SAVING METHOD THEREOF
    • 计算机系统及其节能方法
    • US20080178026A1
    • 2008-07-24
    • US11626622
    • 2007-01-24
    • Jen-Chieh Chen
    • Jen-Chieh Chen
    • G06F1/32
    • G06F1/3203G06F1/3246G06F1/3253G06F1/3287Y02D10/151Y02D10/171
    • A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.
    • 公开了省电方法。 发出停止指令以使得能够从操作状态转换到省电状态。 处理器向芯片组广播消息。 芯片组接收到睡眠消息并进入省电状态,并断言硬件引脚禁用连接处理器和芯片组的数据总线。 确定在功率节省过程中是否向芯片组发出对数据交易的请求。 如果请求被发送到芯片组,则芯片组将硬件引脚置为无效,使能数据总线,将该请求发送给处理器; 并且当数据事务完成时,由芯片组断言硬件引脚以禁止数据总线。