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1. 发明申请

US20140015107A1 METHOD TO IMPROVE WITHIN WAFER UNIFORMITY OF CMP PROCESS 审中-公开
标题翻译：在CMP工艺的WAFER均匀性中改进的方法
公开(公告)号：US20140015107A1
公开(公告)日：2014-01-16
申请号：US13547333
申请日：2012-07-12
申请人： Ching-Kun Chen , Chun-Fu Chen , Chin-Ta Su
发明人： Ching-Kun Chen , Chun-Fu Chen , Chin-Ta Su
IPC分类号： B24B49/14 , H01L29/06 , H01L21/306 , B24B49/02 , B24D3/00
CPC分类号： B24B37/015 , H01L21/3212 , H01L22/12 , H01L22/26
摘要： Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control profile for a chemical mechanical planarization process to more uniformly and consistently achieve the desired extent of variation of within wafer uniformity of a semiconductor wafer.
摘要翻译：可以使用闭环控制来提高使用化学机械平面化的晶片均匀性的均匀性。例如，可以使用闭环控制来确定用于化学机械平面化工艺的控制曲线，以更均匀且一致地实现半导体晶片的晶圆内均匀度期望的变化范围。

2. 发明授权

US08445982B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US08445982B2
公开(公告)日：2013-05-21
申请号：US13156933
申请日：2011-06-09
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.
摘要翻译：公开了多晶硅结构和形成多晶硅结构的方法，其中该方法包括两步沉积和平坦化处理。所公开的方法降低诸如空隙的缺陷的可能性，特别是在具有高纵横比的沟槽中沉积多晶硅时。沉积包括沟槽衬垫部分和第一上部部分的第一多晶硅结构。沟槽衬垫部分仅部分地填充沟槽，而第一上部部分在相邻的隔离结构上延伸。接下来，去除第一多晶硅结构的第一上部的至少一部分。然后沉积包括沟槽塞部分和第二上部部分的第二多晶硅结构。沟槽由插头部分填充，而第二上部部分延伸在相邻的隔离结构上。然后移除第二个上部。

3. 发明申请

US20120313214A1 POLYSILICON STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：多晶硅结构及其制造方法
公开(公告)号：US20120313214A1
公开(公告)日：2012-12-13
申请号：US13156933
申请日：2011-06-09
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.
摘要翻译：公开了多晶硅结构和形成多晶硅结构的方法，其中该方法包括两步沉积和平坦化处理。所公开的方法降低诸如空隙的缺陷的可能性，特别是在具有高纵横比的沟槽中沉积多晶硅时。沉积包括沟槽衬垫部分和第一上部部分的第一多晶硅结构。沟槽衬垫部分仅部分地填充沟槽，而第一上部部分在相邻的隔离结构上延伸。接下来，去除第一多晶硅结构的第一上部的至少一部分。然后沉积包括沟槽塞部分和第二上部部分的第二多晶硅结构。沟槽由插塞部分填充，而第二上部部分延伸在相邻的隔离结构上。然后移除第二个上部。

4. 发明申请

US20090029551A1 Pad and method for chemical mechanical polishing 有权
标题翻译：化学机械抛光垫和方法
公开(公告)号：US20090029551A1
公开(公告)日：2009-01-29
申请号：US11878654
申请日：2007-07-26
申请人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： H01L21/461 , C09K13/00
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

5. 发明申请

US20130241075A1 CONTACT OR VIA CRITICAL DIMENSION CONTROL WITH NOVEL CLOSED LOOP CONTROL SYSTEM IN CHEMICAL MECHANICAL PLANARIZATION PROCESS 审中-公开
标题翻译：联系或通过化学机械平面化过程中的新型闭环控制系统的关键尺寸控制
公开(公告)号：US20130241075A1
公开(公告)日：2013-09-19
申请号：US13418920
申请日：2012-03-13
申请人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
发明人： Chin-Tsan Yeh , Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su
IPC分类号： H01L21/306 , H01L29/30 , B24B49/00
CPC分类号： B24B37/013 , H01L21/3212 , H01L21/7684 , H01L22/12 , H01L22/20
摘要： Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.
摘要翻译：闭环控制可用于通过化学机械平面化改善接触的均匀性或通过临界尺寸。例如，实时闭环控制可用于在化学机械平面化工艺中调节氧化物抛光或过抛光时间，以更均匀且一致地实现半导体晶片的目标临界尺寸。

6. 发明授权

US08047899B2 Pad and method for chemical mechanical polishing 有权
标题翻译：化学机械抛光垫和方法
公开(公告)号：US08047899B2
公开(公告)日：2011-11-01
申请号：US11878654
申请日：2007-07-26
申请人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
发明人： Chun-Fu Chen , Yung-Tai Hung , Chin-Ta Su , Kuang-Chao Chen
IPC分类号： B24B7/22 , B24D3/34
CPC分类号： B24B37/24 , B24D3/346
摘要： A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer.
摘要翻译：提供了半导体器件的两个相邻结构的化学机械抛光方法。一种用于机械抛光的方法，包括：（a）提供半导体器件，其包括在其表面形成的凹部，形成在所述表面上的第一层，以及填充有所述凹部并形成在所述第一层上的第二层; 和（b）用垫和基本上无抑制剂的浆料基本上抛光第一层和第二层，其中该垫包括第二层的腐蚀抑制剂。

7. 发明授权

US08948510B2 Method for merging the regions in the image/video 有权
标题翻译：合并图像/视频中的区域的方法
公开(公告)号：US08948510B2
公开(公告)日：2015-02-03
申请号：US13456286
申请日：2012-04-26
申请人： Gwo Giun (Chris) Lee , He-Yuan Lin , Chun-Fu Chen , Ping-Keng Jao
发明人： Gwo Giun (Chris) Lee , He-Yuan Lin , Chun-Fu Chen , Ping-Keng Jao
IPC分类号： G06K9/34 , G06K9/00 , G06K9/42 , G06K9/44 , G06T7/00
CPC分类号： G06T7/0071 , G06T7/579 , G06T2207/10016 , G06T2207/10024
摘要： The present invention relates to a method for merging regions in the image/video, capable of merging plural of image regions into an image merging region. In the disclosed method, these image regions are first sequenced basing on their compactness value. Then, one of these image regions is designated as a reference image region, and a merging test process is executed by merging the reference image region with one of the nearby image regions thereof in sequence, for forming a temporal image merging region. Later, the compactness value of the temporal image merging region is compared with the compactness value of the two consisting image regions thereof, respectively. When the compactness value of the temporal image merging region is larger than either one of the compactness value of the two consisting image regions thereof, the temporal image merging region is designated as an image merging region.
摘要翻译：本发明涉及一种用于合并图像/视频中的区域的方法，其能够将多个图像区域合并成图像合并区域。在所公开的方法中，这些图像区域首先根据其紧凑度值进行测序。然后，将这些图像区域中的一个指定为参考图像区域，并且通过依次将参考图像区域与其附近的图像区域中的一个合并来执行合并测试处理，以形成时间图像合成区域。然后，将时间图像合成区域的紧凑度值分别与其组成的图像区域的紧凑度值进行比较。当时间图像合并区域的紧凑度值大于其组成图像区域的两个的紧凑度值中的任一个时，时间图像合成区域被指定为图像合并区域。

8. 发明授权

US08482314B2 Method and apparatus for improved multiplexing using tri-state inverter 有权
标题翻译：使用三态逆变器改进复用的方法和装置
公开(公告)号：US08482314B2
公开(公告)日：2013-07-09
申请号：US13291204
申请日：2011-11-08
申请人： Chun-Fu Chen , Hui-Zhong Zhuang , Jen-Hang Yang
发明人： Chun-Fu Chen , Hui-Zhong Zhuang , Jen-Hang Yang
IPC分类号： H03K19/00
CPC分类号： H03K19/1737 , H01L27/0207 , Y10T29/4913
摘要： A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.
摘要翻译：复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。第一和第二堆叠分别包括第一和第二虚拟晶体管。

9. 发明授权

US4091236A Automatically tunable notch filter and method for suppression of acoustical feedback 失效
标题翻译：自动调谐陷波滤波器和抑制声反馈的方法
公开(公告)号：US4091236A
公开(公告)日：1978-05-23
申请号：US720842
申请日：1976-09-07
申请人： Chun-Fu Chen
发明人： Chun-Fu Chen
IPC分类号： H03G5/16 , H04R3/02 , H04M1/20
CPC分类号： H03G5/16 , H04R3/02
摘要： Disclosed is an automatically tunable notch filter and method for suppression of acoustical feedback in an audio signal. The apparatus includes a selectively tunable notch filter having a center frequency which is variable over at least a substantial portion of the audio frequency spectrum. The apparatus receives an audio signal which is substantially non-periodic in the absence of acoustical feedback and substantially periodic with an instantaneous dominant frequency in the presence of the same. The duration of successive periods are monitored and compared by an up/down counter to determine whether the audio input signal is substantially periodic and to determine the instantaneous dominant frequency of such audio signal. Upon detection of an audio signal which is substantially periodic, the notch filter is tuned to the instantaneous dominant frequency so as to suppress the acoustical feedback.
摘要翻译：公开了一种用于抑制音频信号中的声反馈的自动可调陷波滤波器和方法。该装置包括可选择的可调陷波滤波器，其具有可在音频频谱的至少大部分上变化的中心频率。该装置在没有声反馈的情况下接收基本上非周期性的音频信号，并且在存在声音反馈的情况下基本上周期性地具有瞬时主导频率。监视连续周期的持续时间并通过向上/向下计数器进行比较，以确定音频输入信号是否基本上是周期性的并且确定这种音频信号的瞬时主频。在检测到基本周期性的音频信号时，将陷波滤波器调谐到瞬时主频，以抑制声反馈。

10. 发明授权

US08872269B2 Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits 有权
标题翻译：天线电池设计，以防止半导体集成电路中的等离子体感应栅介质损坏
公开(公告)号：US08872269B2
公开(公告)日：2014-10-28
申请号：US13316807
申请日：2011-12-12
申请人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
发明人： Jen-Hang Yang , Chun-Fu Chen , Pin-Dai Sue , Hui-Zhong Zhuang
IPC分类号： H01L21/70
CPC分类号： H01L21/28008 , H01L21/283 , H01L21/76895 , H01L23/60 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
摘要翻译：提供了一种用于防止等离子体增强的栅极介质故障的天线单元。天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。多晶硅引线可以是一组并联的嵌套多晶硅引线之一。虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。二极管与形成有半导体衬底的半导体衬底形成。源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。

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