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    • 9. 发明申请
    • LDMOS device with improved ESD performance
    • LDMOS器件具有改进的ESD性能
    • US20070170469A1
    • 2007-07-26
    • US11337147
    • 2006-01-20
    • Kuo-Ming WuJian-Hsing LeeYi-Chun LinChi-Chih Chen
    • Kuo-Ming WuJian-Hsing LeeYi-Chun LinChi-Chih Chen
    • H01L29/76
    • H01L29/7816H01L29/0696H01L29/0873H01L29/0878H01L29/0882H01L29/4238
    • A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.
    • 半导体器件包括设置在半导体衬底中的第一阱上的第一掺杂区; 第二掺杂区域,其设置在与所述半导体衬底中的所述第一阱相邻的第二阱上,所述第二掺杂区域的掺杂剂密度高于所述第二阱的掺杂剂密度; 以及覆盖第一和第二阱的部分的栅极结构,用于控制在第一和第二掺杂区域之间流动的电流。 从第二掺杂区域和第二阱之间的界面到其栅极结构的最近边缘的第一间隔距离大于从第二掺杂区域的中心点到栅极结构边缘的第二间隔距离的200% 从而增加针对在ESD事件期间在第一和第二掺杂区域之间流动的静电放电(ESD)电流的阻抗。