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1. 发明申请

US20100164062A1 METHOD OF MANUFACTURING THROUGH-SILICON-VIA AND THROUGH-SILICON-VIA STRUCTURE 审中-公开
标题翻译：通过硅晶体和通过硅结构制造方法
公开(公告)号：US20100164062A1
公开(公告)日：2010-07-01
申请号：US12480694
申请日：2009-06-09
申请人： Ching-Chiun Wang , Tai-Yuan Wu , Yu-Sheng Chen , Cha-Hsin Lin
发明人： Ching-Chiun Wang , Tai-Yuan Wu , Yu-Sheng Chen , Cha-Hsin Lin
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L27/0629 , H01L2224/05001 , H01L2224/05009 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/056 , H01L2224/05647 , H01L2224/05684 , H01L2224/13022 , H01L2224/13025 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13157 , H01L2924/00014 , H01L2924/0105 , H01L2924/013
摘要： A method of manufacturing through-silicon-via (TSV) and a TSV structure are provided. The TSV structure includes a silicon substrate, an annular capacitor, a conductive through-via, a layer of low-k material, and a bump. The annular capacitor is within the silicon substrate and constituted of a first conductive layer, a capacitor dielectric layer, and a second conductive layer from the inside to the outside. The conductive through-via is disposed in the silicon substrate surrounded by the annular capacitor, and the layer of low-k material is between the annular capacitor and the conductive through-via. The bump is in touch with the conductive through-via for bonding other chip.
摘要翻译：提供了通过硅通孔（TSV）和TSV结构的方法。 TSV结构包括硅衬底，环形电容器，导电通孔，低k材料层和凸块。环形电容器在硅衬底内，由第一导电层，电容器电介质层和从内向外的第二导电层构成。导电通孔设置在由环形电容器包围的硅衬底中，低k材料层位于环形电容器和导电通孔之间。凸块与用于粘合其他芯片的导电通孔相接触。

2. 发明授权

US07700988B2 Metal-insulator-metal capacitor 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US07700988B2
公开(公告)日：2010-04-20
申请号：US11386362
申请日：2006-03-21
申请人： Cha-Hsin Lin , Ching-Chiun Wang , Lurng-Shehng Lee
发明人： Cha-Hsin Lin , Ching-Chiun Wang , Lurng-Shehng Lee
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/56 , H01L21/02186 , H01L21/022 , H01L21/31604
摘要： A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.
摘要翻译：提供了具有顶部电极，底部电极和电容器电介质层的金属 - 绝缘体金属（MIM）电容器。顶部电极位于底部电极之上，并且电容器介电层设置在顶部和底部电极之间。电容器介电层包括几个氧化钛（TiO 2）层和至少一个四方结构材料层。四方结构材料层设置在两个氧化钛层之间，每个四边形结构材料层具有相同或不同的厚度。可以通过钛氧化物层之间的四方材料层来切断泄漏路径。同时，四方结构材料层可以诱导氧化钛层转变成高k金红石相。

3. 发明申请

US20070141778A1 Metal-insulator-metal capacitor 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US20070141778A1
公开(公告)日：2007-06-21
申请号：US11386362
申请日：2006-03-21
申请人： Cha-Hsin Lin , Ching-Chiun Wang , Lurng-Shehng Lee
发明人： Cha-Hsin Lin , Ching-Chiun Wang , Lurng-Shehng Lee
IPC分类号： H01L21/8242
CPC分类号： H01L28/56 , H01L21/02186 , H01L21/022 , H01L21/31604
摘要： A metal-insulator-metal (MIM) capacitor having a top electrode, a bottom electrode and a capacitor dielectric layer is provided. The top electrode is located over the bottom electrode and the capacitor dielectric layer is disposed between the top and the bottom electrode. The capacitor dielectric layer comprises several titanium oxide (TiO2) layers and at least one tetragonal structure material layer. The tetragonal structure material layer is disposed between two titanium oxide layers and each tetragonal structure material layer has the same or a different thickness. Leakage path can be cut off through the tetragonal material layer between the titanium oxide layers. In the meantime, the tetragonal structure material layer can induce the titanium oxide layers to transform into a high k rutile phase.
摘要翻译：提供了具有顶部电极，底部电极和电容器电介质层的金属 - 绝缘体金属（MIM）电容器。顶部电极位于底部电极之上，并且电容器介电层设置在顶部和底部电极之间。电容器介电层包括几个氧化钛（TiO 2）层和至少一个四方结构材料层。四方结构材料层设置在两个氧化钛层之间，每个四边形结构材料层具有相同或不同的厚度。可以通过钛氧化物层之间的四方材料层来切断泄漏路径。同时，四方结构材料层可以诱导氧化钛层转变成高k金红石相。

4. 发明授权

US08124954B2 Conductive bridging random access memory device and method of manufacturing the same 有权
标题翻译：导电桥接随机存取存储器件及其制造方法
公开(公告)号：US08124954B2
公开(公告)日：2012-02-28
申请号：US12472386
申请日：2009-05-27
申请人： Ching-Chiun Wang , Cha-Hsin Lin
发明人： Ching-Chiun Wang , Cha-Hsin Lin
IPC分类号： H01L29/04
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/146 , Y10T29/417
摘要： A conductive bridging random access memory (CBRAM) device and a method of manufacturing the same are provided. The CBRAM device includes a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer. Since the metal layer is disposed near the solid electrolyte layer in the CBRAM device, it can generate a positive electric field during an erase operation, so as to accelerate a break of mutually connected metal filaments.
摘要翻译：提供了导电桥接随机存取存储器（CBRAM）装置及其制造方法。 CBRAM器件包括第一电极层，电介质层，固体电解质层，第二电极层和金属层。固体电解质层位于第一电极层上。第二电极层位于固体电解质层上。金属层位于固体电解质层附近。电介质层位于固体电解质层和金属层之间。由于金属层设置在CBRAM器件中的固体电解质层附近，所以在擦除操作期间可以产生正电场，从而加速相互连接的金属细丝的断裂。

5. 发明申请

US20070166911A1 BOTTOM ELECTRODE OF METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：金属绝缘子金属电容器的底电极及其制造方法
公开(公告)号：US20070166911A1
公开(公告)日：2007-07-19
申请号：US11308841
申请日：2006-05-15
申请人： Wen-Miao Lo , Lurng-Sheng Lee , Pei-Ren Jeng , Cha-Hsin Lin , Ching-Chiun Wang
发明人： Wen-Miao Lo , Lurng-Sheng Lee , Pei-Ren Jeng , Cha-Hsin Lin , Ching-Chiun Wang
IPC分类号： H01L21/8244
CPC分类号： H01L21/0337 , H01L28/65
摘要： A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.
摘要翻译：提供一种制造金属 - 绝缘体 - 金属（MIM）电容器的底部电极的结构和方法。首先，在基板上形成过渡金属层。此后，在过渡金属层上形成具有纳米图案的自组装聚合物膜，以暴露过渡金属层的一部分。使用自组装聚合物膜作为掩模，过渡金属层的暴露部分被处理以进行相变，使得底部电极可以实现纳米级的相分离。此后，去除自组装聚合物膜。

6. 发明申请

US20070145525A1 MIM CAPACITOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译： MIM电容器结构及其制造方法
公开(公告)号：US20070145525A1
公开(公告)日：2007-06-28
申请号：US11463893
申请日：2006-08-11
申请人： Ching-Chiun Wang , Cha-Hsin Lin , Wen-Miao Lo , Lurng-Shehng Lee
发明人： Ching-Chiun Wang , Cha-Hsin Lin , Wen-Miao Lo , Lurng-Shehng Lee
IPC分类号： H01L29/00
CPC分类号： H01L28/75 , H01L28/65
摘要： A metal-insulator-insulator (MIM) capacitor structure is provided. The MIM capacitor includes a top electrode, a bottom electrode and a dielectric layer. The dielectric layer is disposed between the top electrode and the bottom electrode. The main feature for this kind of MIM capacitor is that the bottom electrode includes a conductive layer and a metal nitride with multi-layered structure. The metal nitride with multi-layered structure is disposed between the conductive layer and the dielectric layer. The nitrogen content in the metal nitride with multi-layered structure gradually increases toward the dielectric layer and the metal nitride belongs to the amorphous type. Due to the presence of the metal nitride, the dielectric layer is prevented from crystallization, thereby reducing the current leakage of the MIM capacitor.
摘要翻译：提供了一种金属绝缘体绝缘体（MIM）电容器结构。 MIM电容器包括顶电极，底电极和电介质层。介电层设置在顶部电极和底部电极之间。这种MIM电容器的主要特征在于，底部电极包括导电层和具有多层结构的金属氮化物。具有多层结构的金属氮化物被设置在导电层和电介质层之间。具有多层结构的金属氮化物中的氮含量朝向电介质层逐渐增加，并且金属氮化物属于非晶型。由于金属氮化物的存在，阻止介电层结晶，从而减少MIM电容器的电流泄漏。

7. 发明申请

US20070122934A1 Silicon-based photodetector and method of fabricating the same 失效
标题翻译：硅基光电探测器及其制造方法
公开(公告)号：US20070122934A1
公开(公告)日：2007-05-31
申请号：US11288900
申请日：2005-11-29
申请人： Cha-Hsin Lin , Lurng-Shehng Lee , Ching-Chiun Wang
发明人： Cha-Hsin Lin , Lurng-Shehng Lee , Ching-Chiun Wang
IPC分类号： H01L21/00
CPC分类号： H01L31/035281 , H01L31/03529 , H01L31/09 , H01L31/108 , Y02E10/50
摘要： A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.
摘要翻译：一种制造光检测器件的方法包括制备硅衬底，在硅衬底上形成图案化的台面，并在图案化的台面上形成图案化的导电层。

8. 发明申请

US20100163829A1 CONDUCTIVE BRIDGING RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：导电桥接随机存取存储器件及其制造方法
公开(公告)号：US20100163829A1
公开(公告)日：2010-07-01
申请号：US12472386
申请日：2009-05-27
申请人： Ching-Chiun Wang , Cha-Hsin Lin
发明人： Ching-Chiun Wang , Cha-Hsin Lin
IPC分类号： H01L47/00 , H01L21/06 , H01L21/36
CPC分类号： H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/146 , Y10T29/417
摘要： A conductive bridging random access memory (CBRAM) device and a method of manufacturing the same are provided. The CBRAM device includes a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer. Since the metal layer is disposed near the solid electrolyte layer in the CBRAM device, it can generate a positive electric field during an erase operation, so as to accelerate a break of mutually connected metal filaments.
摘要翻译：提供了导电桥接随机存取存储器（CBRAM）装置及其制造方法。 CBRAM器件包括第一电极层，电介质层，固体电解质层，第二电极层和金属层。固体电解质层位于第一电极层上。第二电极层位于固体电解质层上。金属层位于固体电解质层附近。电介质层位于固体电解质层和金属层之间。由于金属层设置在CBRAM器件中的固体电解质层附近，所以在擦除操作期间可以产生正电场，从而加速相互连接的金属细丝的断裂。

9. 发明授权

US07683374B2 Silicon based photodetector 失效
标题翻译：硅基光电探测器
公开(公告)号：US07683374B2
公开(公告)日：2010-03-23
申请号：US11288900
申请日：2005-11-29
申请人： Cha-Hsin Lin , Lurng-Shehng Lee , Ching-Chiun Wang
发明人： Cha-Hsin Lin , Lurng-Shehng Lee , Ching-Chiun Wang
IPC分类号： H01L27/108 , H01L29/04 , H01L29/76 , H01L31/062 , H01L31/113
CPC分类号： H01L31/035281 , H01L31/03529 , H01L31/09 , H01L31/108 , Y02E10/50
摘要： A method of fabricating a photodetector device includes preparing a silicon substrate, forming a patterned mesa on the silicon substrate, and forming a patterned conductive layer over the patterned mesa.
摘要翻译：一种制造光检测器件的方法包括制备硅衬底，在硅衬底上形成图案化的台面，并在图案化的台面上形成图案化的导电层。

10. 发明申请

US20080054394A1 RESISTANCE TYPE MEMORY DEVICE 审中-公开
标题翻译：电阻型存储器件
公开(公告)号：US20080054394A1
公开(公告)日：2008-03-06
申请号：US11554591
申请日：2006-10-31
申请人： Cha-Hsin Lin , Ching-Chiun Wang
发明人： Cha-Hsin Lin , Ching-Chiun Wang
IPC分类号： H01L29/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/00 , G11C13/0007 , G11C2213/32 , H01L45/04 , H01L45/1206 , H01L45/1233 , H01L45/146
摘要： A resistance type memory device disposed on a substrate including a first conductive layer, a second conductive layer and a variable resistance material layer is described. These conductive layers are composed of single or separate electrodes. The variable resistance material layer is disposed between the first conductive layer and the second conductive layer.
摘要翻译：描述了设置在包括第一导电层，第二导电层和可变电阻材料层的基板上的电阻型存储器件。这些导电层由单个或单独的电极组成。可变电阻材料层设置在第一导电层和第二导电层之间。

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