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1. 发明申请

US20080238396A1 Feedback controller having multiple feedback paths 有权
标题翻译：反馈控制器具有多个反馈路径
公开(公告)号：US20080238396A1
公开(公告)日：2008-10-02
申请号：US11731167
申请日：2007-03-30
申请人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
发明人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
IPC分类号： G05F1/10 , H03K5/153
CPC分类号： H03K7/08 , H03F3/217 , H03F3/45475
摘要： A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.
摘要翻译：反馈控制器包括第一和第二反馈电路。第一反馈电路连接在输入节点和输出节点之间，并具有错误节点。第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器，以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。所述第二反馈电路连接在所述输入节点和所述误差节点之间，并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器，用于响应于所述反馈信号的值高于或低于一个阈值。

2. 发明授权

US07948224B2 Feedback controller having multiple feedback paths 有权
标题翻译：反馈控制器具有多个反馈路径
公开(公告)号：US07948224B2
公开(公告)日：2011-05-24
申请号：US11731167
申请日：2007-03-30
申请人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
发明人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
IPC分类号： G05F1/00
CPC分类号： H03K7/08 , H03F3/217 , H03F3/45475
摘要： A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.
摘要翻译：反馈控制器包括第一和第二反馈电路。第一反馈电路连接在输入节点和输出节点之间，并具有错误节点。第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器，以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。所述第二反馈电路连接在所述输入节点和所述误差节点之间，并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器，用于响应于所述反馈信号的值在上方或下方来控制所述电流源一个阈值。

3. 发明申请

US20090146749A1 Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch 有权
标题翻译：具有电容比选择占空比的低电压振荡器和S-R锁存器的单输入子阈值导通比较器
公开(公告)号：US20090146749A1
公开(公告)日：2009-06-11
申请号：US11952127
申请日：2007-12-06
申请人： Chik Wai Ng , Yat To Wong , Ho Ming Wan , David Kwok Kuen Kwong
发明人： Chik Wai Ng , Yat To Wong , Ho Ming Wan , David Kwok Kuen Kwong
IPC分类号： H03K3/26
CPC分类号： H03K4/501
摘要： An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.
摘要翻译：振荡器在非常低的电压下工作，但是具有由充电和放电的电容器的比率设定的占空比。子阈值p沟道晶体管导通低于正常阈值电压的次阈值电流，以及设置复位S-R锁存器的驱动器设置和复位输入。 S-R锁存器驱动振荡器输出。振荡器输出反馈给对一个电容器板充电的p沟道晶体管。在半周期中，充电p沟道晶体管截止，允许电容器的一个板通过n沟道放电晶体管放电。在通过电容器的电容确定的放电周期之后，子阈值p沟道晶体管的栅极对于亚阈值电流流下来足以触发S-R锁存器的置位或复位输入。由于需要次阈值电流来切换S-R锁存器，所以振荡器开始振荡低于阈值电压。

4. 发明申请

US20090045867A1 FUSE CELL AND METHOD FOR PROGRAMMING THE SAME 有权
标题翻译：保险丝盒及其编程方法
公开(公告)号：US20090045867A1
公开(公告)日：2009-02-19
申请号：US11838051
申请日：2007-08-13
申请人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
发明人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
IPC分类号： H01H85/00
CPC分类号： G11C17/16 , Y02P80/30
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译：用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。

5. 发明授权

US07538597B2 Fuse cell and method for programming the same 有权
标题翻译：保险丝盒及其编程方法
公开(公告)号：US07538597B2
公开(公告)日：2009-05-26
申请号：US11838051
申请日：2007-08-13
申请人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
发明人： David Kwok Kuen Kwong , Ho Ming Karen Wan , Kam Chuen Wan , Chik Wai Ng
IPC分类号： H03H37/76
CPC分类号： G11C17/16 , Y02P80/30
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译：用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。

6. 发明申请

US20110267008A1 Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
标题翻译：使用电压升压时钟的单功率晶体管电池充电电路
公开(公告)号：US20110267008A1
公开(公告)日：2011-11-03
申请号：US13179107
申请日：2011-07-08
申请人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
发明人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。

7. 发明申请

US20100148727A1 Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
标题翻译：使用电压升压时钟的单功率晶体管电池充电电路
公开(公告)号：US20100148727A1
公开(公告)日：2010-06-17
申请号：US12336514
申请日：2008-12-16
申请人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
发明人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。

8. 发明申请

US20100315748A1 ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs 有权
标题翻译：使用电容耦合钳位保护低压芯片晶体管的ESD保护从高压输出
公开(公告)号：US20100315748A1
公开(公告)日：2010-12-16
申请号：US12481696
申请日：2009-06-10
申请人： Kwok Kuen Kwong , Chik Wai Ng , Wai Kit (Victor) SO , Hing Kit KWAN
发明人： Kwok Kuen Kwong , Chik Wai Ng , Wai Kit (Victor) SO , Hing Kit KWAN
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018557
摘要： An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
摘要翻译：静电放电（ESD）保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源，并在供电时禁用ESD保护电路。施加到输出端的ESD脉冲通过ESD耦合电容器耦合，使耦合栅极节点高电压，并接通栅极 - 接地晶体管，使n沟道输出晶体管的栅极接地，从而分解ESD电流。防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。

9. 发明申请

US20100073070A1 Low Voltage High-Output-Driving CMOS Voltage Reference With Temperature Compensation 有权
标题翻译：具有温度补偿功能的低电压高输出驱动CMOS参考电压
公开(公告)号：US20100073070A1
公开(公告)日：2010-03-25
申请号：US12237500
申请日：2008-09-25
申请人： Chik Wai Ng , Kwok Kuen Kwong
发明人： Chik Wai Ng , Kwok Kuen Kwong
IPC分类号： G05F1/567 , G05F1/10
CPC分类号： G05F3/30
摘要： A bandgap reference voltage generator has a first stage that generates a first current that is complementary-to-absolute-temperature (Ictat) and a second stage that generates a current that is proportional-to-absolute-temperature (Iptat). The Ictat and Iptat currents are both forced through a summing resistor to generate a voltage that is relatively independent of temperature, since the Ictat and Iptat currents cancel out each other's temperature dependencies. A PMOS output transistor drives current to an output load to maintain the load at the reference voltage. An op amp drives the gate of the PMOS output transistor and has inputs connected to emitters of PNP transistors in the second stage. A series of resistors generate the reference voltage between the PMOS output transistor and ground and drives bases of the PNP transistors and includes the summing resistor. Parasitic PNP transistors in an all-CMOS process are used. The generator operates with a 1-volt power supply.
摘要翻译：带隙参考电压发生器具有产生互补绝对温度（Ictat）的第一电流的第一级和产生与绝对温度成比例的电流（Iptat）的第二级。 Ictat和Iptat电流都被强制通过求和电阻产生一个相对独立于温度的电压，因为Ictat和Iptat电流抵消了彼此的温度依赖性。 PMOS输出晶体管将电流驱动到输出负载以将负载保持在参考电压。运算放大器驱动PMOS输出晶体管的栅极，并且在第二级中具有连接到PNP晶体管的发射极的输入。一系列电阻器在PMOS输出晶体管和地之间产生参考电压，并驱动PNP晶体管的基极，并包含求和电阻。使用全CMOS工艺中的寄生PNP晶体管。发电机采用1伏电源供电。

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