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1. 发明授权

US08593199B2 Clock generation method and system 有权
标题翻译：时钟生成方法和系统
公开(公告)号：US08593199B2
公开(公告)日：2013-11-26
申请号：US13476017
申请日：2012-05-21
申请人： Chih-Jou Lin , Yuan-Hsun Chang , Cheng-Ji Chang
发明人： Chih-Jou Lin , Yuan-Hsun Chang , Cheng-Ji Chang
IPC分类号： H03K3/00
CPC分类号： H04L7/041 , G06F1/04 , H03K4/026
摘要： The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.
摘要翻译：时钟生成方法包含以下步骤。在脉冲识别步骤中，首先对输入脉冲信号进行滤波以去除更短的信号。然后，对剩余的脉冲信号进行宽度数字化计算。基于宽度数字化计算，记录信号并确定记录信号的周期。期间的值被传递到增益模块。在验证D / A转换器的输入值的步骤中，从增益模块向D / A转换器输入两个值，并将D / A转换器的输出传送到振荡器。增益模块确定从增益模块到D / A转换器的所需输入值。在脉冲产生步骤中，增益模块将期望的输入值输入到D / A转换器，D / A转换器又传送到振荡器以产生相应的时钟。

2. 发明授权

US07707336B2 Universal serial bus (USB) system with single port and host controller thereof 有权
标题翻译：通用串行总线（USB）系统，具有单端口和主机控制器
公开(公告)号：US07707336B2
公开(公告)日：2010-04-27
申请号：US10906683
申请日：2005-03-02
申请人： Chih-Jou Lin
发明人： Chih-Jou Lin
IPC分类号： G06F5/00 , G06F13/20
CPC分类号： G06F13/385
摘要： A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitry. The speed detection circuitry is electrically coupled to the USB port for detecting a transmission speed between the USB and the external circuitry via the USB port to provide a detecting result. The SOF generator is electrically coupled to the speed detection circuitry for receiving the detecting result and outputting a SOF signal, to determine a cycle of the SOF signal based on the detecting result. The host controller is electrically coupled to the SOF generator and the speed detection circuitry for adjusting the host controller based on SOF signal cycle to comply with the USB 2.0, USB 1.1 and USB 1.0 transmission standards.
摘要翻译：提供具有单端口的通用串行总线（USB）及其主机控制器。 USB包括USB端口，速度检测电路，帧起始（SOF）发生器和主机控制器。 USB端口电耦合到外部电路。速度检测电路电耦合到USB端口，用于通过USB端口检测USB和外部电路之间的传输速度，以提供检测结果。 SOF发生器电耦合到速度检测电路，用于接收检测结果并输出SOF信号，以根据检测结果确定SOF信号的周期。主机控制器电耦合到SOF发生器和速度检测电路，用于基于SOF信号周期调整主机控制器，以符合USB 2.0，USB 1.1和USB 1.0传输标准。

3. 发明申请

US20060064521A1 UNIVERSAL SERIAL BUS (USB) SYSTEM WITH SINGLE PORT AND HOST CONTROLLER THEREOF 有权
标题翻译：通用串行总线（USB）系统与单端口和主机控制器
公开(公告)号：US20060064521A1
公开(公告)日：2006-03-23
申请号：US10906683
申请日：2005-03-02
申请人： Chih-Jou Lin
发明人： Chih-Jou Lin
IPC分类号： G06F3/06
CPC分类号： G06F13/385
摘要： A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitry. The speed detection circuitry is electrically coupled to the USB port for detecting a transmission speed between the USB and the external circuitry via the USB port to provide a detecting result. The SOF generator is electrically coupled to the speed detection circuitry for receiving the detecting result and outputting a SOF signal, to determine a cycle of the SOF signal based on the detecting result. The host controller is electrically coupled to the SOF generator and the speed detection circuitry for adjusting the host controller based on SOF signal cycle to comply with the USB 2.0, USB 1.1 and USB 1.0 transmission standards.
摘要翻译：提供具有单端口的通用串行总线（USB）及其主机控制器。 USB包括USB端口，速度检测电路，帧起始（SOF）发生器和主机控制器。 USB端口电耦合到外部电路。速度检测电路电耦合到USB端口，用于通过USB端口检测USB和外部电路之间的传输速度，以提供检测结果。 SOF发生器电耦合到速度检测电路，用于接收检测结果并输出SOF信号，以根据检测结果确定SOF信号的周期。主机控制器电耦合到SOF发生器和速度检测电路，用于基于SOF信号周期调整主机控制器，以符合USB 2.0，USB 1.1和USB 1.0传输标准。

4. 发明授权

US06578097B1 Method and apparatus for transmitting registered data onto a PCI bus 有权
标题翻译：将注册数据发送到PCI总线上的方法和装置
公开(公告)号：US06578097B1
公开(公告)日：2003-06-10
申请号：US09651423
申请日：2000-08-30
申请人： Chang-Fu Lin , Chih-Jou Lin
发明人： Chang-Fu Lin , Chih-Jou Lin
IPC分类号： G06F100
CPC分类号： G06F13/423 , G06F13/4068
摘要： A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity. The apparatus employee a 2R1W data buffer to send a current phase data and a next phase data one clock cycle ahead of the actual AD activity on PCI bus and use a multiplexer to select the current phase data or the next phase data according to a select signal. The select signal is outputted by a OR gate with IRDY# and TRDY# signals as its inputs. Then, the apparatus use a flip-flop to toggling the output signal of the multiplexer to the PCI bus at the actual AD activity. Therefore, the apparatus of the present invention not only reduce the delay time of manipulating the outgoing signals, but also is implemented with simple architecture.
摘要翻译：提供一种将注册数据发送到PCI总线上的方法和装置，其可以减少操纵输出信号的延迟时间，而不会大大增加电路复杂度。该设备雇员一个2R1W数据缓冲器，用于在PCI总线上的实际AD活动之前一个时钟周期发送当前相位数据和下一个相位数据，并使用多路复用器根据选择信号选择当前相位数据或下一个相位数据。选择信号由IRDY＃和TRDY＃信号作为其输入的或门输出。然后，该设备使用触发器在实际的AD活动下切换多路复用器的输出信号到PCI总线。因此，本发明的装置不仅减少了操纵输出信号的延迟时间，而且还以简单的架构来实现。

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