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1. 发明授权

US06408073B1 Scramble circuit to protect data in a read only memory 有权
标题翻译：扰码电路保护只读存储器中的数据
公开(公告)号：US06408073B1
公开(公告)日：2002-06-18
申请号：US09229584
申请日：1999-01-13
申请人： Chih-Jen Hsu , Yuh-Chin Huang , Mu-Chi Hsu
发明人： Chih-Jen Hsu , Yuh-Chin Huang , Mu-Chi Hsu
IPC分类号： H04N7167
CPC分类号： G06F21/79
摘要： A scramble circuit for protecting data stored in a read only memory is provided including an initial value generator, a shift register, a logic circuit, an adder and a lock circuit. In said scramble circuit, the initial value generator is used to generate an initial value. The shift register is used to selectively load in the initial value and the data stored in the read only memory. The logic circuit is used to process the data stored in the shift register to generate an output transmitted back to the shift register. The adder is used to add the data stored in the read only memory and the data stored in the shift register having the same lengths, so as to obtain scrambled data. The lock circuit is used to output or lock the scrambled data according to a lock signal.
摘要翻译：提供一种用于保护存储在只读存储器中的数据的加扰电路，包括初始值生成器，移位寄存器，逻辑电路，加法器和锁定电路。在所述加扰电路中，初始值发生器用于产生初始值。移位寄存器用于选择性地加载初始值和存储在只读存储器中的数据。逻辑电路用于处理存储在移位寄存器中的数据，以产生传输回移位寄存器的输出。加法器用于将存储在只读存储器中的数据和存储在具有相同长度的移位寄存器中的数据相加，以获得加扰数据。锁定电路用于根据锁定信号输出或锁定加扰数据。

2. 发明授权

US08046645B2 Bad block identifying method for flash memory, storage system, and controller thereof 有权
标题翻译：闪存，存储系统及其控制器的坏块识别方法
公开(公告)号：US08046645B2
公开(公告)日：2011-10-25
申请号：US12140090
申请日：2008-06-16
申请人： Chih-Jen Hsu , Yi-Hsiang Huang
发明人： Chih-Jen Hsu , Yi-Hsiang Huang
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G06F11/1068 , G11C16/3454 , G11C29/52 , G11C29/82
摘要： A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.
摘要翻译：提供了一种用于闪速存储器，存储系统及其控制器的坏块识别方法。坏块识别方法包括在块被编程之后确定在闪存的块中是否发生编程错误，并且当编程错误在块中连续出现时将块标记为坏块。由于仅当块中重复发生编程错误时才将块确定为坏块，所以可以避免闪速存储器中坏块的错误判断，从而可以延长闪存存储系统的寿命。

3. 发明申请

US20080010397A1 Flash memory with simulating system and method thereof 审中-公开
标题翻译：具有模拟系统的闪存及其方法
公开(公告)号：US20080010397A1
公开(公告)日：2008-01-10
申请号：US11482738
申请日：2006-07-10
申请人： Jen-Chieh Lou , Chih-Jen Hsu
发明人： Jen-Chieh Lou , Chih-Jen Hsu
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , G06F2212/2022
摘要： The invention presents a multi-type flash memory with simulating system and a method thereof. Meanwhile the method includes the steps of a) providing a simulating circuit data for the multi-type flash memory; b) transforming the simulating circuit data into a programmable circuit device; c) connecting a flash memory access interface of the multi-type flash memory with a first host system; d) connecting a large-scale access interface of the multi-type flash memory with a second host system; e) transmitting data signals between a buffer register of the multi-type flash memory and the first/second host systems via the flash memory access interface/the large-scale access interface; and f) transmitting control signal between the buffer register and the first/second host systems via the programmable circuit device and the flash memory access interface/the large-scale access interface, thereby incorporating a simulating system into the multi-type flash memory conveniently.
摘要翻译：本发明提供一种具有模拟系统的多型闪存及其方法。同时，该方法包括以下步骤：a）提供多类型闪速存储器的模拟电路数据; b）将模拟电路数据转换成可编程电路装置; c）将多类型闪速存储器的闪存存取接口与第一主机系统连接; d）将多型闪存的大规模访问接口与第二主机系统连接; e）经由闪速存储器访问接口/大规模访问接口在多类型闪速存储器的缓冲寄存器与第一/第二主机系统之间传送数据信号; 以及f）经由可编程电路装置和闪存存取接口/大规模存取接口在缓冲寄存器与第一/第二主机系统之间发送控制信号，由此将模拟系统方便地结合到多型闪存中。

4. 发明授权

US5239761A Multiple-purpose measuring instrument 失效
标题翻译：多用途测量仪器
公开(公告)号：US5239761A
公开(公告)日：1993-08-31
申请号：US747270
申请日：1991-08-19
申请人： Chyi-Yiing Wu , Chih-Jen Hsu
发明人： Chyi-Yiing Wu , Chih-Jen Hsu
IPC分类号： G01B5/24 , G01C9/28 , G01C15/10
CPC分类号： G01C9/28 , G01B5/24 , G01C15/10
摘要： A measuring instrument includes a casing served as a rule, an angular level secured in a central portion of the casing having a rotational protractor rotatably mounted in the level for measuring any angles, a horizontal gauge provided in a right side portion of the casing for checking a horizontality, a vertical gauge formed in a left side portion of the casing for checking a verticality, a reelable plummet provided in the casing and protruded outwardly for checking a vertical line or plane, a measuring tape wound in the casing and pulled outwardly for measuring a length, and a protractor template rotatably secured on the casing having a plurality of guide slots of many geometric shapes punched in the template for guiding the drawing of many geometric shapes and having a plurality of angular graduations circularly formed on a pivotal portion of the template also for measuring planar angles, so as to provide a measuring instrument having multiple measurement uses.
摘要翻译：测量仪器包括一般规定的外壳，固定在壳体的中心部分的角度水平仪，其具有可旋转地安装在用于测量任何角度的水平面中的旋转量角器，设置在壳体的右侧部分中的水平仪器用于检查水平度，形成在用于检查垂直度的壳体的左侧部分中的垂直计量器，设置在壳体中并向外突出以用于检查垂直线或平面的可卷绕的出口，卷绕在壳体中并向外拉伸以测量的卷尺长度和量角器模板，其可旋转地固定在壳体上，具有在模板中冲压的许多几何形状的多个引导槽，用于引导许多几何形状的绘图，并且具有圆形地形成在模板的枢转部分上的多个角度刻度也用于测量平面角度，以便提供具有多个测量用途的测量仪器。

5. 发明申请

US20090182932A1 METHOD FOR MANAGING FLASH MEMORY BLOCKS AND CONTROLLER USING THE SAME 审中-公开
标题翻译：用于管理闪速存储器块的方法和使用其的控制器
公开(公告)号：US20090182932A1
公开(公告)日：2009-07-16
申请号：US12053778
申请日：2008-03-24
申请人： Wee-Tah Tan , Jiunn-Yeong Yang , Chih-Jen Hsu , Wee-Kuan Gan
发明人： Wee-Tah Tan , Jiunn-Yeong Yang , Chih-Jen Hsu , Wee-Kuan Gan
IPC分类号： G06F12/02
CPC分类号： G11C29/88 , G11C29/76 , G11C29/765
摘要： A method for managing blocks is provided. In the method, a plurality of flash memories is divided into a plurality of block program units, and blocks mapped to each of the block program units are recorded, wherein each of the block program units maps to at least two blocks. Next, available states of the block program units are respectively determined according to good or bad states of the mapped blocks. Final, good blocks within the block program units are recorded, so as to provide the good blocks within the block program units according to the record for being written with data. Accordingly, it is possible to fully utilize the blocks in the flash memories.
摘要翻译：提供了一种用于管理块的方法。在该方法中，将多个闪速存储器划分为多个块程序单元，并且记录映射到每个块程序单元的块，其中每个块程序单元映射到至少两个块。接下来，块程序单元的可用状态分别根据映射块的好状态或坏状态来确定。最终，记录块程序单元内的好的块，以便根据用于写入数据的记录在块程序单元内提供好的块。因此，可以充分利用闪存中的块。

6. 发明授权

US07319360B2 Modulator 有权
标题翻译：调制器
公开(公告)号：US07319360B2
公开(公告)日：2008-01-15
申请号：US11163729
申请日：2005-10-28
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56
摘要： The present invention describes a modulator including a differential amplifier connected to a reference voltage and a first transistor, and the first transistor is connected to a feedback device, and a second transistor is set between the first transistor and the differential amplifier and connected to a voltage detector and a diode, and the diode is connected to a power supply, and the voltage detector keeps on detecting an output voltage (VOUT) between the feedback device and the first transistor. If the output voltage (VOUT) value is lower than a predetermined voltage value of the power supply, the voltage detector will issue a signal to drive the second transistor and limit a gate-source voltage (VGS) of the first transistor within a voltage difference of the diode, so as to reduce the impetus of the first transistor and avoid the phenomenon of a sudden climb with an excessively large output voltage (VOUT).
摘要翻译：本发明描述了一种包括连接到参考电压的差分放大器和第一晶体管的调制器，并且第一晶体管连接到反馈装置，并且第二晶体管被设置在第一晶体管和差分放大器之间并连接到电压检测器和二极管，并且二极管连接到电源，并且电压检测器继续检测反馈装置和第一晶体管之间的输出电压（VOUT）。如果输出电压（VOUT）值低于电源的预定电压值，则电压检测器将发出一个信号来驱动第二晶体管，并将第一晶体管的栅极 - 源极电压（VGS）限制在一个电压差的二极管，以减少第一晶体管的动力，避免突然上升的现象，输出电压（VOUT）过大。

7. 发明申请

US20070266297A1 CONTROLLER AND STORAGE DEVICE HAVING THE SAME 有权
标题翻译：具有该控制器和存储设备的控制器和存储设备
公开(公告)号：US20070266297A1
公开(公告)日：2007-11-15
申请号：US11758016
申请日：2007-06-05
申请人： Ming-Jen Liang , Wee-Kuan Gan , Chih-Jen Hsu
发明人： Ming-Jen Liang , Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G11C29/04
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0×FF data in the data area and writes all 0×FF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0×FF data and the all 0×FF error-correcting codes into all 0×00 data and all 0×00 error-correcting codes, respectively.
摘要翻译：提供一种用于控制具有纠错码区域和数据区域的非易失性存储器的访问的控制器。控制器包括纠错模块和电连接到纠错模块的第一反相电路，用于反相数据和对应于该数据的纠错码。当控制器都将数据区中的所有0xFF数据写入数据区，并将所有0xFF纠错码写入纠错码区时，第一反相电路将所有0xFF数据和所有0xFF纠错码反转为全部0x00数据，所有0x00纠错码分别。

8. 发明申请

US20060031739A1 CONVERTING CIRCUITFORPREVENTING WRONG ERRORCORRECTION CODES FROM OCCURRING DUE TO AN ERROR CORRECTION RULE DURINGDATA READING OPERATION 有权
标题翻译：由于错误修正规则而导致的错误错误代码的转换电路读取操作
公开(公告)号：US20060031739A1
公开(公告)日：2006-02-09
申请号：US10710860
申请日：2004-08-09
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1068
摘要： A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0×FF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0×FF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0×FF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0×FF.
摘要翻译：提供了一种用于在数据读取操作期间由于纠错规则而发生错误纠错码的转换电路。当闪速存储器控制器将所有0xFF数据写入闪速存储器时，字节纠错规则产生一组正确的纠错码，并且纠错码转换电路将正确的纠错码集合转换为0xFF纠错码，并将值存储在闪速存储器的数据区域和纠错码区域中的数据被转换为0xFF，以防止在纠错码不是完全0xFF时在数据读取操作期间发生错误的纠错码。

9. 发明授权

US08706952B2 Flash memory storage device, controller thereof, and data programming method thereof 有权
标题翻译：闪存存储装置及其控制器及其数据编程方法
公开(公告)号：US08706952B2
公开(公告)日：2014-04-22
申请号：US12766265
申请日：2010-04-23
申请人： Chih-Jen Hsu , Yi-Hsiang Huang , Chung-Lin Wu
发明人： Chih-Jen Hsu , Yi-Hsiang Huang , Chung-Lin Wu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C11/34 , G11C16/04 , G11C7/00
CPC分类号： G06F12/00 , G06F12/02 , G06F12/06
摘要： A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks.
摘要翻译：提供一种闪速存储器存储装置，其控制器和数据编程方法。闪速存储器存储设备具有包括多个物理块的闪存，每个物理块包括多个物理地址，并且物理地址包括至少一个快速物理地址和至少一个慢物理地址。该方法包括至少将物理块分组成数据区和备用区; 设定预定的块号; 从备用区获取m个物理块，接收包括写数据和逻辑地址的写命令，根据逻辑地址和预定块号确定缓冲器的逻辑地址范围。当要写入数据的所有逻辑地址都在缓冲区的逻辑地址范围内时，使用快速模式将数据编程到m个物理块中。

10. 发明授权

US08219883B2 Data accessing method, controller and storage system using the same 有权
标题翻译：数据访问方式，控制器和存储系统使用相同
公开(公告)号：US08219883B2
公开(公告)日：2012-07-10
申请号：US12165123
申请日：2008-06-30
申请人： Chih-Jen Hsu , Yi-Hsiang Huang
发明人： Chih-Jen Hsu , Yi-Hsiang Huang
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G06F11/1004
摘要： Data accessing method for a flash memory, and a controller and a storage system using the same are provided. The data accessing method includes reading data from a physical address of a flash memory according to a physical address to be read corresponding to a logical address to be read in a read command, and determining whether or not the read physical address is the physical address to be read. The data accessing method also includes transmitting the data only if the read physical address is the physical address to be read. Accordingly, it is possible to ensure the transmitted data is data to be accessed by the read command.
摘要翻译：提供了一种用于闪速存储器的数据访问方法，以及使用其的控制器和存储系统。数据存取方法包括根据要读取的要读取的逻辑地址的要读取的物理地址从闪速存储器的物理地址读取数据，以及确定读取的物理地址是否为物理地址被阅读数据访问方法还包括仅当读取的物理地址是要读取的物理地址时才发送数据。因此，可以确保发送的数据是通过读取命令访问的数据。

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