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1. 发明申请

US20090182932A1 METHOD FOR MANAGING FLASH MEMORY BLOCKS AND CONTROLLER USING THE SAME 审中-公开
标题翻译：用于管理闪速存储器块的方法和使用其的控制器
公开(公告)号：US20090182932A1
公开(公告)日：2009-07-16
申请号：US12053778
申请日：2008-03-24
申请人： Wee-Tah Tan , Jiunn-Yeong Yang , Chih-Jen Hsu , Wee-Kuan Gan
发明人： Wee-Tah Tan , Jiunn-Yeong Yang , Chih-Jen Hsu , Wee-Kuan Gan
IPC分类号： G06F12/02
CPC分类号： G11C29/88 , G11C29/76 , G11C29/765
摘要： A method for managing blocks is provided. In the method, a plurality of flash memories is divided into a plurality of block program units, and blocks mapped to each of the block program units are recorded, wherein each of the block program units maps to at least two blocks. Next, available states of the block program units are respectively determined according to good or bad states of the mapped blocks. Final, good blocks within the block program units are recorded, so as to provide the good blocks within the block program units according to the record for being written with data. Accordingly, it is possible to fully utilize the blocks in the flash memories.
摘要翻译：提供了一种用于管理块的方法。在该方法中，将多个闪速存储器划分为多个块程序单元，并且记录映射到每个块程序单元的块，其中每个块程序单元映射到至少两个块。接下来，块程序单元的可用状态分别根据映射块的好状态或坏状态来确定。最终，记录块程序单元内的好的块，以便根据用于写入数据的记录在块程序单元内提供好的块。因此，可以充分利用闪存中的块。

2. 发明授权

US07319360B2 Modulator 有权
标题翻译：调制器
公开(公告)号：US07319360B2
公开(公告)日：2008-01-15
申请号：US11163729
申请日：2005-10-28
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56
摘要： The present invention describes a modulator including a differential amplifier connected to a reference voltage and a first transistor, and the first transistor is connected to a feedback device, and a second transistor is set between the first transistor and the differential amplifier and connected to a voltage detector and a diode, and the diode is connected to a power supply, and the voltage detector keeps on detecting an output voltage (VOUT) between the feedback device and the first transistor. If the output voltage (VOUT) value is lower than a predetermined voltage value of the power supply, the voltage detector will issue a signal to drive the second transistor and limit a gate-source voltage (VGS) of the first transistor within a voltage difference of the diode, so as to reduce the impetus of the first transistor and avoid the phenomenon of a sudden climb with an excessively large output voltage (VOUT).
摘要翻译：本发明描述了一种包括连接到参考电压的差分放大器和第一晶体管的调制器，并且第一晶体管连接到反馈装置，并且第二晶体管被设置在第一晶体管和差分放大器之间并连接到电压检测器和二极管，并且二极管连接到电源，并且电压检测器继续检测反馈装置和第一晶体管之间的输出电压（VOUT）。如果输出电压（VOUT）值低于电源的预定电压值，则电压检测器将发出一个信号来驱动第二晶体管，并将第一晶体管的栅极 - 源极电压（VGS）限制在一个电压差的二极管，以减少第一晶体管的动力，避免突然上升的现象，输出电压（VOUT）过大。

3. 发明申请

US20070266297A1 CONTROLLER AND STORAGE DEVICE HAVING THE SAME 有权
标题翻译：具有该控制器和存储设备的控制器和存储设备
公开(公告)号：US20070266297A1
公开(公告)日：2007-11-15
申请号：US11758016
申请日：2007-06-05
申请人： Ming-Jen Liang , Wee-Kuan Gan , Chih-Jen Hsu
发明人： Ming-Jen Liang , Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G11C29/04
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0×FF data in the data area and writes all 0×FF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0×FF data and the all 0×FF error-correcting codes into all 0×00 data and all 0×00 error-correcting codes, respectively.
摘要翻译：提供一种用于控制具有纠错码区域和数据区域的非易失性存储器的访问的控制器。控制器包括纠错模块和电连接到纠错模块的第一反相电路，用于反相数据和对应于该数据的纠错码。当控制器都将数据区中的所有0xFF数据写入数据区，并将所有0xFF纠错码写入纠错码区时，第一反相电路将所有0xFF数据和所有0xFF纠错码反转为全部0x00数据，所有0x00纠错码分别。

4. 发明申请

US20060031739A1 CONVERTING CIRCUITFORPREVENTING WRONG ERRORCORRECTION CODES FROM OCCURRING DUE TO AN ERROR CORRECTION RULE DURINGDATA READING OPERATION 有权
标题翻译：由于错误修正规则而导致的错误错误代码的转换电路读取操作
公开(公告)号：US20060031739A1
公开(公告)日：2006-02-09
申请号：US10710860
申请日：2004-08-09
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1068
摘要： A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0×FF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0×FF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0×FF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0×FF.
摘要翻译：提供了一种用于在数据读取操作期间由于纠错规则而发生错误纠错码的转换电路。当闪速存储器控制器将所有0xFF数据写入闪速存储器时，字节纠错规则产生一组正确的纠错码，并且纠错码转换电路将正确的纠错码集合转换为0xFF纠错码，并将值存储在闪速存储器的数据区域和纠错码区域中的数据被转换为0xFF，以防止在纠错码不是完全0xFF时在数据读取操作期间发生错误的纠错码。

5. 发明授权

US07263649B2 Converting circuit for preventing wrong error correction codes from occurring due to an error correction rule during data reading operation 有权
标题翻译：用于防止在数据读取操作期间由于纠错规则而发生错误纠错码的转换电路
公开(公告)号：US07263649B2
公开(公告)日：2007-08-28
申请号：US10710860
申请日：2004-08-09
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： H03M13/37
CPC分类号： G06F11/1068
摘要： A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0xFF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and the error correction code converting circuit converts the set of correct error correction codes into 0xFF error correction codes, and values stored in the data area and error correction code area of the flash memory are converted into 0xFF to prevent wrong error correction code from occurring during data reading operation when the error correction codes are not completely 0xFF.
摘要翻译：提供了一种用于在数据读取操作期间由于纠错规则而发生错误纠错码的转换电路。当闪速存储器控制器将所有0xFF数据写入闪速存储器时，字节纠错规则产生一组正确的纠错码，并且纠错码转换电路将正确的纠错码集合转换为0xFF纠错码，并将值存储在闪速存储器的数据区域和纠错码区域中的数据被转换为0xFF，以防止在纠错码不是完全0xFF时在数据读取操作期间发生错误的纠错码。

6. 发明授权

US07949929B2 Controller and storage device having the same 有权
标题翻译：控制器和存储设备具有相同的功能
公开(公告)号：US07949929B2
公开(公告)日：2011-05-24
申请号：US11758016
申请日：2007-06-05
申请人： Ming-Jen Liang , Wee-Kuan Gan , Chih-Jen Hsu
发明人： Ming-Jen Liang , Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0xFF data in the data area and writes all 0xFF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0xFF data and the all 0xFF error-correcting codes into all 0x00 data and all 0x00 error-correcting codes, respectively.
摘要翻译：提供一种用于控制具有纠错码区域和数据区域的非易失性存储器的访问的控制器。控制器包括纠错模块和电连接到纠错模块的第一反相电路，用于反相数据和对应于该数据的纠错码。当控制器都将数据区中的所有0xFF数据写入数据区，并将所有0xFF纠错码写入纠错码区时，第一反相电路将所有0xFF数据和所有0xFF纠错码反转为全部0x00数据，所有0x00纠错码分别。

7. 发明授权

US07276889B2 Detect/modulate circuit 有权
标题翻译：检测/调制电路
公开(公告)号：US07276889B2
公开(公告)日：2007-10-02
申请号：US11163517
申请日：2005-10-21
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G05F1/40
CPC分类号： G05F3/30
摘要： A detect/modulate circuit comprises a plurality of modulate resistors connected to a main resistor of a bandgap in series, and each module resistor is connected to a transistor switch in parallel, and each transistor switch is connected to a logic controller, and the logic controller is connected in sequence to a plurality of detect circuits and fuses corresponding to the quantity of the transistor switches. When the detect circuit receives a low-to-high power-on reset signal to detect whether or not the fuse is fused, the detect circuit will issue a voltage level signal “0” for the fuse being not fused or a voltage level signal “1” for the fuse being fused to the logic controller. The logic controller converts the received voltage level signal according to a logic conversion table to control the electric connection of the corresponding transistor switch, so as to fine turn the main resistance of the bandgap.
摘要翻译：检测/调制电路包括串联连接到带隙的主电阻器的多个调制电阻器，并且每个模块电阻器并联连接到晶体管开关，并且每个晶体管开关连接到逻辑控制器，并且逻辑控制器被依次连接到多个检测电路和对应于晶体管开关量的保险丝。当检测电路接收到低电平上电复位信号以检测熔丝是否熔断时，检测电路将为未熔断的熔丝发出电压电平信号“0”，或者发出电压电平信号“ 1“，保险丝熔断到逻辑控制器。逻辑控制器根据逻辑转换表转换接收的电压电平信号，以控制相应的晶体管开关的电连接，从而微调带隙的主电阻。

8. 发明申请

US20070090823A1 [DETECT/MODULATE CIRCUIT] 有权
标题翻译： [DETECT / MODULATE CIRCUIT]
公开(公告)号：US20070090823A1
公开(公告)日：2007-04-26
申请号：US11163517
申请日：2005-10-21
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A detect/modulate circuit comprises a plurality of modulate resistors connected to a main resistor of a bandgap in series, and each module resistor is connected to a transistor switch in parallel, and each transistor switch is connected to a logic controller, and the logic controller is connected in sequence to a plurality of detect circuits and fuses corresponding to the quantity of the transistor switches. When the detect circuit receives a low-to-high power-on reset signal to detect whether or not the fuse is fused, the detect circuit will issue a voltage level signal “0” for the fuse being not fused or a voltage level signal “1” for the fuse being fused to the logic controller. The logic controller converts the received voltage level signal according to a logic conversion table to control the electric connection of the corresponding transistor switch, so as to fine turn the main resistance of the bandgap.
摘要翻译：检测/调制电路包括串联连接到带隙的主电阻器的多个调制电阻器，并且每个模块电阻器并联连接到晶体管开关，并且每个晶体管开关连接到逻辑控制器，并且逻辑控制器被依次连接到多个检测电路和对应于晶体管开关量的保险丝。当检测电路接收到低电平上电复位信号以检测熔丝是否熔断时，检测电路将为未熔断的熔丝发出电压电平信号“0”，或者发出电压电平信号“ 1“，保险丝熔断到逻辑控制器。逻辑控制器根据逻辑转换表转换接收的电压电平信号，以控制相应的晶体管开关的电连接，从而微调带隙的主电阻。

9. 发明申请

US20060267673A1 [MODULATOR] 有权
标题翻译： [调制器]
公开(公告)号：US20060267673A1
公开(公告)日：2006-11-30
申请号：US11163729
申请日：2005-10-28
申请人： Wee-Kuan Gan , Chih-Jen Hsu
发明人： Wee-Kuan Gan , Chih-Jen Hsu
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： The present invention describes a modulator including a differential amplifier connected to a reference voltage and a first transistor, and the first transistor is connected to a feedback device, and a second transistor is set between the first transistor and the differential amplifier and connected to a voltage detector and a diode, and the diode is connected to a power supply, and the voltage detector keeps on detecting an output voltage (VOUT) between the feedback device and the first transistor. If the output voltage (VOUT) value is lower than a predetermined voltage value of the power supply, the voltage detector will issue a signal to drive the second transistor and limit a gate-source voltage (VGS) of the first transistor within a voltage difference of the diode, so as to reduce the impetus of the first transistor and avoid the phenomenon of a sudden climb with an excessively large output voltage (VOUT).
摘要翻译：本发明描述了一种包括连接到参考电压的差分放大器和第一晶体管的调制器，并且第一晶体管连接到反馈装置，并且第二晶体管被设置在第一晶体管和差分放大器之间并连接到电压检测器和二极管，并且二极管连接到电源，并且电压检测器继续检测反馈装置和第一晶体管之间的输出电压（VOUT）。如果输出电压（VOUT）值低于电源的预定电压值，则电压检测器将发出一个信号来驱动第二晶体管，并将第一晶体管的栅极 - 源极电压（VGS）限制在一个电压差的二极管，以减少第一晶体管的动力，避免突然上升的现象，输出电压（VOUT）过大。

10. 发明授权

US08046645B2 Bad block identifying method for flash memory, storage system, and controller thereof 有权
标题翻译：闪存，存储系统及其控制器的坏块识别方法
公开(公告)号：US08046645B2
公开(公告)日：2011-10-25
申请号：US12140090
申请日：2008-06-16
申请人： Chih-Jen Hsu , Yi-Hsiang Huang
发明人： Chih-Jen Hsu , Yi-Hsiang Huang
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G06F11/1068 , G11C16/3454 , G11C29/52 , G11C29/82
摘要： A bad block identifying method for a flash memory, a storage system, and a controller thereof are provided. The bad block identifying method includes determining whether a programming error occurs in a block of the flash memory after the block is programmed and marking the block as a bad block when the programming error successively occurs in the block. Since the block is determined to be a bad block only when the programming error repeatedly occurs in the block, misjudgment of bad block in the flash memory can be avoided and accordingly the lifespan of the flash memory storage system can be prolonged.
摘要翻译：提供了一种用于闪速存储器，存储系统及其控制器的坏块识别方法。坏块识别方法包括在块被编程之后确定在闪存的块中是否发生编程错误，并且当编程错误在块中连续出现时将块标记为坏块。由于仅当块中重复发生编程错误时才将块确定为坏块，所以可以避免闪速存储器中坏块的错误判断，从而可以延长闪存存储系统的寿命。

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