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1. 发明申请

US20070117353A1 Method for Forming Oxide on Ono Structure 有权
标题翻译：在小结构上形成氧化物的方法
公开(公告)号：US20070117353A1
公开(公告)日：2007-05-24
申请号：US11625177
申请日：2007-01-19
申请人： Chih Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L29/94 , H01L21/326
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

2. 发明授权

US07183166B2 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US07183166B2
公开(公告)日：2007-02-27
申请号：US10721605
申请日：2003-11-25
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

3. 发明授权

US07919372B2 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US07919372B2
公开(公告)日：2011-04-05
申请号：US11625177
申请日：2007-01-19
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

4. 发明申请

US20050110102A1 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US20050110102A1
公开(公告)日：2005-05-26
申请号：US10721605
申请日：2003-11-25
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/316 , H01L21/28 , H01L21/314 , H01L21/318 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

5. 发明授权

US07241558B2 Multi-layer semiconductor integrated circuits enabling stabilizing photolithography process parameters, the photomask being used, and the manufacturing method thereof 有权
标题翻译：能够稳定光刻工艺参数的多层半导体集成电路，所使用的光掩模及其制造方法
公开(公告)号：US07241558B2
公开(公告)日：2007-07-10
申请号：US10284327
申请日：2002-10-31
申请人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang , Jia-Rong Chiou
发明人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang , Jia-Rong Chiou
IPC分类号： G03C5/00
CPC分类号： G03F1/36 , G03F7/70433 , G03F7/70441
摘要： Stabilization of photolithography process parameters, the photomask being used, and the manufacturing method thereof is provided where a formal pattern layout is combined with a dummy pattern. A photomask is manufactured by utilizing the combined pattern layout so that density changes between the pattern structure layers of the multi-layer semiconductor integrated circuits are minimized.
摘要翻译：提供了光刻工艺参数的稳定化，所使用的光掩模及其制造方法，其中形式图案布局与虚拟图案组合。通过利用组合的图案布局制造光掩模，使得多层半导体集成电路的图案结构层之间的密度变化最小化。

6. 发明授权

US06531393B2 Salicide integrated solution for embedded virtual-ground memory 有权
公开(公告)号：US06531393B2
公开(公告)日：2003-03-11
申请号：US09760597
申请日：2001-01-16
申请人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang
发明人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang
IPC分类号： H01L2144
CPC分类号： H01L27/112 , H01L21/743 , H01L27/105 , H01L27/11286
摘要： A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.

7. 发明授权

US06413861B1 Method of fabricating a salicide of an embedded memory 有权
标题翻译：一种嵌入式存储器的杀虫剂的制造方法
公开(公告)号：US06413861B1
公开(公告)日：2002-07-02
申请号：US09836210
申请日：2001-04-18
申请人： Chong-Jen Huang , Hsin-Huei Chen , Chih-Hao Wang , Kuang-Wen Liu
发明人： Chong-Jen Huang , Hsin-Huei Chen , Chih-Hao Wang , Kuang-Wen Liu
IPC分类号： H01L2144
CPC分类号： H01L27/11568 , H01L21/76897 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/11573 , H01L29/665
摘要： A memory array region and a periphery circuit region are defined on a silicon substrate of a semiconductor wafer. A plurality of gates is formed on the silicon substrate in both the memory array region and the periphery circuit region. A barrier layer and a dielectric layer are formed, respectively, on the semiconductor wafer. Therein, the barrier layer covers the gates and the barrier layer fills a space between two gates. Following that, the dielectric layer atop each gate is removed and the dielectric layer remaining in the space between two gates is aligned to the surface of the gates. A photoresist layer is formed to cover the memory array region followed by an etching process to remove the dielectric layer and the barrier layer down to the surface of the silicon substrate. The photoresist layer and the barrier layer atop the gate in the memory array region are removed. Finally, a salicide process is performed.
摘要翻译：存储器阵列区域和外围电路区域被限定在半导体晶片的硅衬底上。在存储器阵列区域和外围电路区域中的硅衬底上形成多个栅极。分别在半导体晶片上形成阻挡层和电介质层。其中，阻挡层覆盖栅极，势垒层填充两个栅极之间的空间。之后，去除每个栅极顶部的电介质层，并且残留在两个栅极之间的空间中的电介质层与栅极的表面对准。形成光致抗蚀剂层以覆盖存储器阵列区域，随后进行蚀刻工艺以将电介质层和阻挡层向下移动到硅衬底的表面。除去存储器阵列区域中的栅极顶部的光致抗蚀剂层和阻挡层。最后，执行一个自杀过程。

8. 发明授权

US07923770B2 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07923770B2
公开(公告)日：2011-04-12
申请号：US12140064
申请日：2008-06-16
申请人： Chih-Lin Chen , Kuang-Wen Liu , Hsin-Huei Chen
发明人： Chih-Lin Chen , Kuang-Wen Liu , Hsin-Huei Chen
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.
摘要翻译：提供一种制造存储器件的方法。首先，依次在基板上形成包括栅介电结构的电荷存储结构，以形成电荷捕获层。然后，在电荷存储结构的上方形成栅极导电层。之后，栅极导电层和电荷存储结构的至少一部分被图案化。图案化电荷存储结构的横截面然后变成梯形或梯形模拟物，其在栅极导电层附近具有较短的一侧，在衬底附近具有较长的一侧。

9. 发明申请

US20080042191A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080042191A1
公开(公告)日：2008-02-21
申请号：US11465885
申请日：2006-08-21
申请人： Cheng-Wei Lin , Kuang-Wen Liu , Hsin-Huei Chen
发明人： Cheng-Wei Lin , Kuang-Wen Liu , Hsin-Huei Chen
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory device is provided. The method includes forming a plurality of trenches in a substrate. The trenches are filled with first conducting layers to serve as buried bit lines. Thereafter, a charge storage layer is formed on the substrate to cover the surface of the substrate and the first conducting layers. A plurality of second conducting layers is formed on the charge storage layer to serve as word lines.
摘要翻译：提供一种制造非易失性存储器件的方法。该方法包括在衬底中形成多个沟槽。沟槽填充有用作掩埋位线的第一导电层。此后，在基板上形成电荷存储层以覆盖基板的表面和第一导电层。在电荷存储层上形成多个第二导电层以用作字线。

10. 发明申请

US20090146266A1 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20090146266A1
公开(公告)日：2009-06-11
申请号：US12140064
申请日：2008-06-16
申请人： Chih-Lin Chen , Kuang-Wen Liu , Hsin-Huei Chen
发明人： Chih-Lin Chen , Kuang-Wen Liu , Hsin-Huei Chen
IPC分类号： H01L29/00 , H01L21/306 , H01L21/308
CPC分类号： H01L21/28282 , H01L29/4234 , H01L29/792
摘要： A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.
摘要翻译：提供一种制造存储器件的方法。首先，依次在基板上形成包括栅介电结构的电荷存储结构，以形成电荷捕获层。然后，在电荷存储结构的上方形成栅极导电层。之后，栅极导电层和电荷存储结构的至少一部分被图案化。图案化电荷存储结构的横截面然后变成梯形或梯形模拟物，其在栅极导电层附近具有较短的一侧，在衬底附近具有较长的一侧。

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