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1. 发明授权

US07183166B2 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US07183166B2
公开(公告)日：2007-02-27
申请号：US10721605
申请日：2003-11-25
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

2. 发明申请

US20050110102A1 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US20050110102A1
公开(公告)日：2005-05-26
申请号：US10721605
申请日：2003-11-25
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/316 , H01L21/28 , H01L21/314 , H01L21/318 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

3. 发明授权

US07919372B2 Method for forming oxide on ONO structure 有权
标题翻译：在ONO结构上形成氧化物的方法
公开(公告)号：US07919372B2
公开(公告)日：2011-04-05
申请号：US11625177
申请日：2007-01-19
申请人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih-Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

4. 发明申请

US20070117353A1 Method for Forming Oxide on Ono Structure 有权
标题翻译：在小结构上形成氧化物的方法
公开(公告)号：US20070117353A1
公开(公告)日：2007-05-24
申请号：US11625177
申请日：2007-01-19
申请人： Chih Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
发明人： Chih Hao Wang , Hsin-Huei Chen , Chong-Jen Huang , Kuang-Wen Liu , Jia-Rong Chiou , Chong-Mu Chen
IPC分类号： H01L29/94 , H01L21/326
CPC分类号： H01L21/022 , H01L21/02164 , H01L21/0217 , H01L21/28282 , H01L21/3144 , H01L29/66833 , Y10S438/954
摘要： A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures. Exposing the patterned silicon nitride to the oxygen radical during the RTO according to the invention significantly reduces the processing time, and reduces the thermal budget. Moreover, because according to the invention the upper surface and the sidewalls of the silicon nitride layer are covered by the top oxide layer, the silicon nitride is not exposed during a subsequent cleaning process. As a result of increased contact area between the polysilicon gate and the top oxide layer, the coupling ratio of the gate is increased.
摘要翻译：通过在具有存储区域和逻辑器件区域的衬底上提供第一氧化硅层和氮化硅层来形成具有氧化硅/氮化硅/氧化硅（“ONO”）结构的半导体器件; 图案化第一氧化硅层和氮化硅层以限定部分完成的ONO堆叠的底部氧化物和氮化硅部分并且暴露逻辑器件区域中的衬底; 在自由基氧化剂的存在下进行快速热退火工艺，以在氮化硅层的暴露表面和衬底上的栅氧化层上同时形成第二氧化硅层; 以及在完成的ONO堆叠和栅极氧化物上沉积导电层。本发明用于制造例如具有外围逻辑器件的存储器件和包括ONO结构的存储器单元。根据本发明，在RTO期间将图案化的氮化硅暴露于氧自由基显着减少了处理时间，并降低了热预算。此外，由于根据本发明，氮化硅层的上表面和侧壁被顶部氧化物层覆盖，所以在随后的清洁过程中氮化硅不暴露。由于多晶硅栅极和顶部氧化物层之间的接触面积增加，栅极的耦合比增加。

5. 发明授权

US07241558B2 Multi-layer semiconductor integrated circuits enabling stabilizing photolithography process parameters, the photomask being used, and the manufacturing method thereof 有权
标题翻译：能够稳定光刻工艺参数的多层半导体集成电路，所使用的光掩模及其制造方法
公开(公告)号：US07241558B2
公开(公告)日：2007-07-10
申请号：US10284327
申请日：2002-10-31
申请人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang , Jia-Rong Chiou
发明人： Chong-Jen Huang , Hsin-Huei Chen , Kuang-Wen Liu , Chih-Hao Wang , Jia-Rong Chiou
IPC分类号： G03C5/00
CPC分类号： G03F1/36 , G03F7/70433 , G03F7/70441
摘要： Stabilization of photolithography process parameters, the photomask being used, and the manufacturing method thereof is provided where a formal pattern layout is combined with a dummy pattern. A photomask is manufactured by utilizing the combined pattern layout so that density changes between the pattern structure layers of the multi-layer semiconductor integrated circuits are minimized.
摘要翻译：提供了光刻工艺参数的稳定化，所使用的光掩模及其制造方法，其中形式图案布局与虚拟图案组合。通过利用组合的图案布局制造光掩模，使得多层半导体集成电路的图案结构层之间的密度变化最小化。

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