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1. 发明授权

US08395195B2 Bottom-notched SiGe FinFET formation using condensation 有权
标题翻译：底部缺口SiGe使用冷凝的FinFET形成
公开(公告)号：US08395195B2
公开(公告)日：2013-03-12
申请号：US12702862
申请日：2010-02-09
申请人： Chih-Hao Chang , Jeffrey Junhao Xu , Chien-Hsun Wang , Chih-Hsiang Chang
发明人： Chih-Hao Chang , Jeffrey Junhao Xu , Chien-Hsun Wang , Chih-Hsiang Chang
IPC分类号： H01L27/085
CPC分类号： H01L29/66795 , H01L29/7853
摘要： An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
摘要翻译：集成电路结构包括在衬底上的衬底和含锗半导体鳍。含锗半导体翅片具有第一宽度的上部和在上部下方的颈部区域，并且具有小于第一宽度的第二宽度。

2. 发明申请

US20110193178A1 Bottom-Notched SiGe FinFET Formation Using Condensation 有权
标题翻译：使用冷凝的底部缺陷SiGe FinFET形成
公开(公告)号：US20110193178A1
公开(公告)日：2011-08-11
申请号：US12702862
申请日：2010-02-09
申请人： Chih-Hao Chang , Jeffrey Junhao Xu , Chien-Hsun Wang , Chih-Hsiang Chang
发明人： Chih-Hao Chang , Jeffrey Junhao Xu , Chien-Hsun Wang , Chih-Hsiang Chang
IPC分类号： H01L29/78 , H01L29/24
CPC分类号： H01L29/66795 , H01L29/7853
摘要： An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
摘要翻译：集成电路结构包括在衬底上的衬底和含锗半导体鳍。含锗半导体翅片具有第一宽度的上部和在上部下方的颈部区域，并且具有小于第一宽度的第二宽度。

3. 发明授权

US08623728B2 Method for forming high germanium concentration SiGe stressor 有权
标题翻译：形成高锗浓度SiGe应激源的方法
公开(公告)号：US08623728B2
公开(公告)日：2014-01-07
申请号：US12831842
申请日：2010-07-07
申请人： Chih-Hao Chang , Jeff J. Xu , Chien-Hsun Wang , Chih Chieh Yeh , Chih-Hsiang Chang
发明人： Chih-Hao Chang , Jeff J. Xu , Chien-Hsun Wang , Chih Chieh Yeh , Chih-Hsiang Chang
IPC分类号： H01L21/336 , H01L21/31 , H01L21/469 , H01L21/00
CPC分类号： H01L29/785 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/18 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/66795 , H01L29/7848
摘要： A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.
摘要翻译：提供了具有高Ge浓度的SiGe应激源的制造方法。该方法包括：提供具有源极区域，漏极区域和沟道之间的半导体衬底; 在源极区域和/或漏极区域上沉积第一SiGe膜层; 进行低温热氧化，例如高水蒸气压湿氧化，以在第一SiGe层的顶部形成氧化物层，并在第一SiGe膜的底部形成具有高Ge百分比的第二SiGe膜层 Ge层扩散到半导体衬底中; 执行热扩散以从第二SiGe膜层形成SiGe应力源，其中SiGe应力源在通道上提供单轴压缩应变; 并除去氧化物层。在进行氧化之前，可以在第一SiGe膜层上淀积Si覆盖层。

4. 发明申请

US20110241084A1 Semiconductor Device with a Buried Stressor 有权
标题翻译：具有埋入应力的半导体器件
公开(公告)号：US20110241084A1
公开(公告)日：2011-10-06
申请号：US12750160
申请日：2010-03-30
申请人： Zhiqiang Wu , Jeffrey Junhao Xu , Chih-Hao Chang , Wen-Hsing Hsieh
发明人： Zhiqiang Wu , Jeffrey Junhao Xu , Chih-Hao Chang , Wen-Hsing Hsieh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.
摘要翻译：提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。凹槽形成在栅电极的相对侧上。沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。

5. 发明授权

US08338259B2 Semiconductor device with a buried stressor 有权
标题翻译：具有埋地应力的半导体器件
公开(公告)号：US08338259B2
公开(公告)日：2012-12-25
申请号：US12750160
申请日：2010-03-30
申请人： Zhiqiang Wu , Jeffrey Junhao Xu , Chih-Hao Chang , Wen-Hsing Hsieh
发明人： Zhiqiang Wu , Jeffrey Junhao Xu , Chih-Hao Chang , Wen-Hsing Hsieh
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7848
摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.
摘要翻译：提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。凹槽形成在栅电极的相对侧上。沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。

6. 发明授权

US08935452B2 Connector assembly 有权
标题翻译：连接器组件
公开(公告)号：US08935452B2
公开(公告)日：2015-01-13
申请号：US13039271
申请日：2011-03-02
申请人： Mao-Shun Hsi , Yau-Shi Hwang , Chih-Hao Chang , Po-Nien Wang
发明人： Mao-Shun Hsi , Yau-Shi Hwang , Chih-Hao Chang , Po-Nien Wang
IPC分类号： G06F13/00 , H01R11/00 , H01R12/72
CPC分类号： H01R12/721
摘要： A connector assembly for connecting a peripheral device to a computer includes a male connector having a plurality of first connecting pins and a female connector having a plurality of second connecting pins. The plurality of first connecting pins is configured to connect to the peripheral device. The plurality of second connecting pins is configured to connect to the computer. The plurality of second connecting pins is defined on the first circuit board in a second row and a third row. The plurality of second connecting pins comprises a plurality of differential pairs, and each differential pair comprises two differential transmission lines. The two differential transmission lines of each of the plurality of differential pairs are defined on a single row of the second and third rows.
摘要翻译：用于将外围设备连接到计算机的连接器组件包括具有多个第一连接引脚的阳连接器和具有多个第二连接引脚的阴连接器。多个第一连接引脚被配置为连接到外围设备。多个第二连接销被配置为连接到计算机。多个第二连接销被限定在第二行和第三行的第一电路板上。多个第二连接引脚包括多个差分对，并且每个差分对包括两个差分传输线。多个差分对中的每一个的两个差分传输线被限定在第二行和第三行的单行上。

7. 发明授权

US08804065B2 Flexible liquid crystal display and flexible fluid display 有权
标题翻译：灵活的液晶显示和柔性流体显示
公开(公告)号：US08804065B2
公开(公告)日：2014-08-12
申请号：US13346400
申请日：2012-01-09
申请人： Tarng-Shiang Hu , Yi-Kai Wang , Yu-Jung Peng , Tsung-Hua Yang , Chih-Hao Chang
发明人： Tarng-Shiang Hu , Yi-Kai Wang , Yu-Jung Peng , Tsung-Hua Yang , Chih-Hao Chang
IPC分类号： G02F1/1333 , G02F1/1339
CPC分类号： G02B26/005 , G02F1/133305 , G02F1/133377 , G02F1/13394 , G02F2001/13396
摘要： A flexible liquid crystal display and a flexible fluid display are provided. The flexible liquid crystal display includes a first module, a second module, at least two supporting structures and a liquid crystal layer. The second module is disposed correspondingly to the first module. The supporting structures are separately disposed between the first module and the second module and used for abutting the first module and the second module, so that a space between the first module and the second module is divided into a flexible area and two non-flexible areas. The flexible area is located between the two non-flexible areas. The liquid crystal layer is disposed in the flexible area and the two non-flexible areas.
摘要翻译：提供柔性液晶显示器和柔性流体显示器。柔性液晶显示器包括第一模块，第二模块，至少两个支撑结构和液晶层。第二模块相对于第一模块设置。所述支撑结构分别设置在所述第一模块和所述第二模块之间，并且用于邻接所述第一模块和所述第二模块，使得所述第一模块和所述第二模块之间的空间被分成柔性区域和两个非柔性区域。柔性区域位于两个非柔性区域之间。液晶层设置在柔性区域和两个非柔性区域中。

8. 发明授权

US08759920B2 Semiconductor device and method of forming the same 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US08759920B2
公开(公告)日：2014-06-24
申请号：US13486343
申请日：2012-06-01
申请人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
发明人： Clement Hsingjen Wann , Chih-Hao Chang , Shou Zen Chang , Chih-Hsin Ko , Yasutoshi Okuno , Andrew Joseph Kelly
IPC分类号： H01L21/70
CPC分类号： H01L21/823814 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。常见的接触特征是自对准接触。

9. 发明授权

US08727601B2 Display for electronic device 有权
标题翻译：显示电子设备
公开(公告)号：US08727601B2
公开(公告)日：2014-05-20
申请号：US13334977
申请日：2011-12-22
申请人： Yi-Kai Wang , Tsung-Hua Yang , Tarng-Shiang Hu , Chih-Hao Chang , Yu-Jung Peng
发明人： Yi-Kai Wang , Tsung-Hua Yang , Tarng-Shiang Hu , Chih-Hao Chang , Yu-Jung Peng
IPC分类号： G09F13/08
CPC分类号： G09F9/30 , G09F9/301
摘要： A display includes a flexible display panel having a back face, two backlight modules disposed on the back face of the display panel and each including a contact end, and an outer casing having two casing panels respectively connected to and supporting the backlight modules oppositely of the display panel. The casing panels are pivotal to move the backlight modules and the display panel between collapsed and non-collapsed positions. In the collapsed position, the display panel is folded, and the backlight modules are parallelly spaced apart. In the non-collapsed position, the display panel is laid flat, the backlight modules coplanarly cover the back face of the display panel, and the contact ends of the backlight modules abut against each other.
摘要翻译：显示器包括具有背面的柔性显示面板，设置在显示面板的背面上的两个背光模块，每个包括接触端，以及具有两个壳体面板的外壳，两个外壳面板分别连接到背光模块显示面板。壳体面板枢转以将背光模块和显示面板在折叠位置和非折叠位置之间移动。在折叠位置，显示面板被折叠，并且背光模块平行间隔开。在未折叠位置，显示面板平坦化，背光模块共面地覆盖显示面板的背面，背光模块的接触端部彼此抵接。

10. 发明授权

US08513912B2 Power supply circuit 失效
标题翻译：电源电路
公开(公告)号：US08513912B2
公开(公告)日：2013-08-20
申请号：US13086239
申请日：2011-04-13
申请人： Mao-Shun Hsi , Yau-Shi Hwang , Chih-Hao Chang , Chung-Chih Chou , Po-Nien Wang
发明人： Mao-Shun Hsi , Yau-Shi Hwang , Chih-Hao Chang , Chung-Chih Chou , Po-Nien Wang
IPC分类号： H01M6/50 , H02J7/00
CPC分类号： H02J7/0032
摘要： A power supply circuit for protecting a battery from current leakage when the battery is not in use includes a control signal input circuit and a switch circuit. The control signal input circuit receives a first control signal from a chip and output a second control signal. The switch circuit receives the second control signal and turns on or off an electronic connection between the battery and the chip. Wherein when the battery is not in use and not being charged by the adaptor, there is a possibility of current leakage from the battery. In such case, the switch circuit turns off the electronic connection between the battery and the chip, and the battery does not provide power to the chip.
摘要翻译：当不使用电池时，用于保护电池免受电流泄漏的电源电路包括控制信号输入电路和开关电路。控制信号输入电路从芯片接收第一控制信号并输出第二控制信号。开关电路接收第二控制信号并打开或关闭电池和芯片之间的电子连接。其中，当电池未使用并且未被适配器充电时，存在来自电池的电流泄漏的可能性。在这种情况下，开关电路关闭电池和芯片之间的电子连接，并且电池不向芯片供电。

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