专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08183913B2 Integrated circuits including a charge pump circuit and operating methods thereof 有权
标题翻译：包括电荷泵电路的集成电路及其操作方法
公开(公告)号：US08183913B2
公开(公告)日：2012-05-22
申请号：US12706886
申请日：2010-02-17
申请人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven Swei , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

2. 发明授权

US08575966B2 Method of operating phase-lock assistant circuitry 有权
标题翻译：操作锁相辅助电路的方法
公开(公告)号：US08575966B2
公开(公告)日：2013-11-05
申请号：US13718235
申请日：2012-12-18
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.
摘要翻译：操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。电荷泵电路根据上升信号和下降信号进行驱动。

3. 发明授权

US08354862B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译：包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于输入信号。电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是晚于输入信号。电路还包括被配置为产生第一增加信号的第三电路。电路还包括被配置为产生第一减小信号的第四电路。

4. 发明授权

US08179162B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

5. 发明授权

US08068576B2 Counters and exemplary applications 有权
标题翻译：计数器和示范应用
公开(公告)号：US08068576B2
公开(公告)日：2011-11-29
申请号：US12699458
申请日：2010-02-03
申请人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
发明人： Chih-Chang Lin , Tien-Chun Yang , Steven Swei
IPC分类号： H03K21/00
CPC分类号： H03K21/38
摘要： Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.
摘要翻译：本文描述的实施例涉及计数器。在一些实施例中，计数器可以用作分频器，例如在分数PLL中。在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。对于计数器C1计数到N1，N1被加载到计数器C1。类似地，对于计数器C2计数到N2，N2被加载到计数器C2。当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。

6. 发明申请

US20110199152A1 INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括充电泵电路及其工作方法
公开(公告)号：US20110199152A1
公开(公告)日：2011-08-18
申请号：US12706886
申请日：2010-02-17
申请人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

7. 发明授权

US07961050B1 Integrated circuits including an equalizer and operating methods thereof 有权
标题翻译：集成电路，包括均衡器及其操作方法
公开(公告)号：US07961050B1
公开(公告)日：2011-06-14
申请号：US12706872
申请日：2010-02-17
申请人： Yuwen Swei , Tien-Chun Yang , Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang
发明人： Yuwen Swei , Tien-Chun Yang , Chih-Chang Lin , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： H03F3/04
CPC分类号： H03F3/45197 , H03F3/45183 , H03F3/45192 , H03F2203/45292 , H03F2203/45458 , H03F2203/45496 , H03F2203/45562 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45702
摘要： An integrated circuit includes a differential amplifier. The differential amplifier includes at least one output end. A circuit is coupled with the at least one output end of the differential amplifier. The circuit does not include a resistor-capacitor (RC) network and is configured for providing a negative impedance to the differential amplifier for adjusting a direct current (DC) gain of the integrated circuit.
摘要翻译：集成电路包括差分放大器。差分放大器包括至少一个输出端。电路与差分放大器的至少一个输出端耦合。该电路不包括电阻 - 电容（RC）网络，并被配置为向差分放大器提供负阻抗以调整集成电路的直流（DC）增益。

8. 发明授权

US08324960B2 Charge pump doubler 有权
标题翻译：电荷泵倍增器
公开(公告)号：US08324960B2
公开(公告)日：2012-12-04
申请号：US12849503
申请日：2010-08-03
申请人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin , Tien-Chun Yang , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Chih-Chang Lin , Tien-Chun Yang , Yuwen Swei
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07
摘要： An integrated circuit includes a first PMOS transistor, where its drain is arranged to be coupled to a voltage output, and its source is coupled to the drain of a second PMOS transistor. The source of the second PMOS transistor is arranged to be coupled to a high power supply voltage. The source and drain of a MOS capacitor are coupled to the source of the first PMOS transistor. The drain of an NMOS transistor is coupled to the drain of the first PMOS transistor. The integrated circuit is configured to receive a voltage input to generate the voltage output having a maximum voltage higher than the voltage input. The gate oxide layer thickness of the MOS capacitor is less than that of the first PMOS transistor.
摘要翻译：集成电路包括第一PMOS晶体管，其中其漏极被布置成耦合到电压输出，并且其源极耦合到第二PMOS晶体管的漏极。第二PMOS晶体管的源极被布置成耦合到高电源电压。 MOS电容器的源极和漏极耦合到第一PMOS晶体管的源极。 NMOS晶体管的漏极耦合到第一PMOS晶体管的漏极。集成电路被配置为接收电压输入以产生具有高于电压输入的最大电压的电压输出。 MOS电容器的栅氧化层厚度小于第一PMOS晶体管的栅极氧化层厚度。

9. 发明授权

US08223576B2 Regulators regulating charge pump and memory circuits thereof 有权
标题翻译：调节电荷泵及其存储电路的调节器
公开(公告)号：US08223576B2
公开(公告)日：2012-07-17
申请号：US12716430
申请日：2010-03-03
申请人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
发明人： Tien-Chun Yang , Chih-Chang Lin , Ming-Chieh Huang
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C11/4074
摘要： A regulator for regulating a charge pump is provided. The regulator includes a comparator having a first input end capable of receiving a first voltage and a second input end capable of receiving a second voltage for determining enabling or disabling the charge pump. The first voltage is associated with an output voltage of the charge pump. The second voltage is associated with an internal power voltage and a reference voltage Vref.
摘要翻译：提供了一种用于调节电荷泵的调节器。调节器包括具有能够接收第一电压的第一输入端和能够接收用于确定启动或禁用电荷泵的第二电压的第二输入端的比较器。第一电压与电荷泵的输出电压相关联。第二电压与内部电源电压和参考电压Vref相关联。

10. 发明授权

US09489989B2 Voltage regulators, memory circuits, and operating methods thereof 有权
标题翻译：电压调节器，存储器电路及其操作方法
公开(公告)号：US09489989B2
公开(公告)日：2016-11-08
申请号：US12820712
申请日：2010-06-22
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
IPC分类号： G11C11/22 , G11C11/24 , G11C7/06 , G11C5/14 , G11C8/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.
摘要翻译：电压调节器包括与电压调节器的输出端电耦合的输出级。输出级包括具有体积和漏极的至少一个晶体管。至少一个背偏置电路与所述至少一个晶体管的主体电耦合。至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式