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1. 发明申请

US20120012904A1 METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：金属氧化物半导体晶体管及其制造方法
公开(公告)号：US20120012904A1
公开(公告)日：2012-01-19
申请号：US12837475
申请日：2010-07-15
申请人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
发明人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66689 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/7816 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
摘要翻译：公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

2. 发明授权

US08816409B2 Metal-oxide semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管
公开(公告)号：US08816409B2
公开(公告)日：2014-08-26
申请号：US12837475
申请日：2010-07-15
申请人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
发明人： Ming-Te Wei , Wen-Chen Wu , Lung-En Kuo , Po-Chao Tsao
IPC分类号： H01L21/00 , H01L29/165 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66689 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/165 , H01L29/6656 , H01L29/66575 , H01L29/66636 , H01L29/7816 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
摘要翻译：公开了一种用于制造金属氧化物半导体（MOS）晶体管的方法。该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成硅层; 在硅层上进行第一光蚀刻工艺以形成栅极图案; 在与栅极图案的两侧相邻的半导体衬底中形成外延层; 以及对所述栅极图案执行第二光蚀刻处理以在所述栅极图案中形成槽，同时使用所述栅极图案将所述栅极图案物理分离成两个栅极。

3. 发明授权

US08524608B1 Method for fabricating a patterned structure of a semiconductor device 有权
标题翻译：用于制造半导体器件的图案化结构的方法
公开(公告)号：US08524608B1
公开(公告)日：2013-09-03
申请号：US13456245
申请日：2012-04-26
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Hsuan-Hsu Chen , Meng-Chun Lee
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Hsuan-Hsu Chen , Meng-Chun Lee
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/0337 , H01L21/28123 , H01L21/3086 , H01L21/32139
摘要： The present invention provides a method for fabricating a patterned structure in a semiconductor device, which includes the following processes. First, a target layer, a first mask and a first patterned mask are sequentially formed on a substrate. Then, a first etching process is performed to form a plurality of characteristic structures on the substrate, wherein each of the characteristic structures comprises a patterned first mask and a patterned target layer. A second patterned mask is formed on the substrate, wherein the second patterned mask covers a portion of the characteristic structures and exposes a predetermined region. A second etching process is performed to fully eliminate the characteristic structures within the predetermined region. Finally, a third etching process is performed to fully eliminate the target layer not covered by the patterned first mask.
摘要翻译：本发明提供一种在半导体器件中制造图案化结构的方法，其包括以下处理。首先，在基板上依次形成目标层，第一掩模和第一图案化掩模。然后，执行第一蚀刻工艺以在衬底上形成多个特征结构，其中每个特征结构包括图案化的第一掩模和图案化目标层。第二图案化掩模形成在衬底上，其中第二图案化掩模覆盖特征结构的一部分并暴露预定区域。执行第二蚀刻处理以完全消除预定区域内的特征结构。最后，执行第三蚀刻处理以完全消除未被图案化的第一掩模覆盖的目标层。

4. 发明授权

US07851370B2 Patterning method 有权
标题翻译：图案化方法
公开(公告)号：US07851370B2
公开(公告)日：2010-12-14
申请号：US11860792
申请日：2007-09-25
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76224 , H01L22/26
摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
摘要翻译：提供了图案化方法。在图案化方法中，在基板上形成膜，并测量预层信息。接下来，进行蚀刻处理以蚀刻该膜。蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设置用于进行延长蚀刻步骤的延长蚀刻时间，以获得所需的膜轮廓。

5. 发明申请

US20090258500A1 METHOD OF FORMING A PATTERN FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE RELATED MOS TRANSISTOR 有权
标题翻译：形成半导体器件的图案的方法和形成相关MOS晶体管的方法
公开(公告)号：US20090258500A1
公开(公告)日：2009-10-15
申请号：US12101122
申请日：2008-04-10
申请人： Min-Chieh Yang , Lung-En Kuo
发明人： Min-Chieh Yang , Lung-En Kuo
IPC分类号： H01L21/311
CPC分类号： H01L21/3081 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
摘要翻译：一种形成半导体器件的图案的方法，其中在上部旋涂玻璃（SOG）层和下部蚀刻目标层之间包括两个硬掩模。 SOG层分别通过两个不同的图案化光致抗蚀剂蚀刻两次以在SOG层中形成精细图案。随后，通过利用图案化的SOG层作为蚀刻掩模来蚀刻上部硬掩模，因此上部图案化的硬掩模可以具有声音形状和足够厚度的精细图案。此后，通过利用上部图案化的硬掩模作为蚀刻掩模来蚀刻下部硬掩模和蚀刻目标层，因此可以很好地保护被两个硬掩模覆盖的蚀刻目标层的部分免受蚀刻处理。

6. 发明申请

US20130295738A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130295738A1
公开(公告)日：2013-11-07
申请号：US13463809
申请日：2012-05-03
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Hsuan-Hsu Chen
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Hsuan-Hsu Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.
摘要翻译：半导体工艺包括以下步骤。在基板上形成翅片状结构。形成栅极结构和盖层，其中栅极结构设置在鳍状结构的一部分和基板的一部分之间，盖层在栅极结构上，并且盖层包括第一盖层栅极结构和第一盖层上的第二盖层。形成间隔材料以完全覆盖第二盖层，鳍状结构和基底。间隔物材料被蚀刻，使得第二盖层的侧壁被暴露，并且在栅极结构旁边形成间隔物。第二盖层被去除。

7. 发明授权

US08329594B2 Method for fabricating a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US08329594B2
公开(公告)日：2012-12-11
申请号：US12851550
申请日：2010-08-05
申请人： Lung-En Kuo
发明人： Lung-En Kuo
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/28123
摘要： A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.
摘要翻译：公开了一种制造半导体结构的方法。该方法包括以下步骤：提供衬底; 在衬底上沉积材料层; 在所述材料层上形成至少一个电介质层; 在介电层上形成图案化的抗蚀剂; 对至少所述图案化抗蚀剂进行第一修整处理; 在至少介电层上进行第二修整处理; 并使用电介质层作为蚀刻材料层的掩模。

8. 发明申请

US20130093062A1 SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
标题翻译：半导体结构及其工艺
公开(公告)号：US20130093062A1
公开(公告)日：2013-04-18
申请号：US13276306
申请日：2011-10-18
申请人： Ying-Chih Lin , Hsuan-Hsu Chen , Jiunn-Hsiung Liao , Lung-En Kuo
发明人： Ying-Chih Lin , Hsuan-Hsu Chen , Jiunn-Hsiung Liao , Lung-En Kuo
IPC分类号： H01L29/02 , H01L21/302
CPC分类号： H01L21/311 , H01L21/3083 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/7851
摘要： A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.
摘要翻译：半导体结构包括基板，凹部和材料。凹部位于基板中，其中凹部具有上部和下部。上部的最小宽度大于下部的最大宽度。材料位于凹槽中。

9. 发明申请

US20090081817A1 PATTERNING METHOD 有权
标题翻译：绘图方法
公开(公告)号：US20090081817A1
公开(公告)日：2009-03-26
申请号：US11860792
申请日：2007-09-25
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Min-Chieh Yang
IPC分类号： H01L21/66
CPC分类号： H01L21/76224 , H01L22/26
摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
摘要翻译：提供了图案化方法。在图案化方法中，在基板上形成膜，并测量预层信息。接下来，进行蚀刻处理以蚀刻该膜。蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设定用于进行延长蚀刻步骤的延长蚀刻时间，以便获得所需的膜轮廓。

10. 发明授权

US08691652B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08691652B2
公开(公告)日：2014-04-08
申请号：US13463809
申请日：2012-05-03
申请人： Lung-En Kuo , Jiunn-Hsiung Liao , Hsuan-Hsu Chen
发明人： Lung-En Kuo , Jiunn-Hsiung Liao , Hsuan-Hsu Chen
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795
摘要： A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.
摘要翻译：半导体工艺包括以下步骤。在基板上形成翅片状结构。形成栅极结构和盖层，其中栅极结构设置在鳍状结构的一部分和基板的一部分之间，盖层在栅极结构上，并且盖层包括第一盖层栅极结构和第一盖层上的第二盖层。形成间隔材料以完全覆盖第二盖层，鳍状结构和基底。间隔物材料被蚀刻，使得第二盖层的侧壁被暴露，并且在栅极结构旁边形成间隔物。第二盖层被去除。

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