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1. 发明授权

US08304871B2 Exposed die package for direct surface mounting 有权
标题翻译：暴露的裸片封装，用于直接表面安装
公开(公告)号：US08304871B2
公开(公告)日：2012-11-06
申请号：US13080320
申请日：2011-04-05
申请人： Frank Yu , Lance Wright , Chien-Te Feng , Sandra Horton
发明人： Frank Yu , Lance Wright , Chien-Te Feng , Sandra Horton
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49541 , H01L24/29 , H01L24/48 , H01L24/73 , H01L2224/2919 , H01L2224/30181 , H01L2224/30505 , H01L2224/30519 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/01019 , H01L2924/1305 , H01L2924/1461 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.
摘要翻译：封装的半导体器件包括半导体管芯，该半导体管芯包括具有包括有源电路的顶面的基板和具有直接附接的至少一个背侧金属层的底部底部。包括具有管芯焊盘和多个引线的成型材料的封装被封装在模制材料内，其中引线包括包括结合部分的暴露部分。半导体管芯的顶侧附接到管芯焊盘，并且封装件包括沿着封装的底表面暴露背面金属层的间隙。键合线将半导体芯片顶端的引线耦合到引线。接合部分，沿着封装的底表面的成型材料和背面金属层彼此基本上是平面的。

2. 发明申请

US20100283142A1 MOLD LOCK ON HEAT SPREADER 有权
标题翻译：模具锁在散热器上
公开(公告)号：US20100283142A1
公开(公告)日：2010-11-11
申请号：US12463729
申请日：2009-05-11
申请人： Chien-Te FENG , Frank Yu
发明人： Chien-Te FENG , Frank Yu
IPC分类号： H01L23/34 , H01L21/56
CPC分类号： H01L23/3107 , H01L21/4878 , H01L23/3142 , H01L23/4334 , H01L23/562 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A mold lock and a method of forming the mold lock are provided. The mold lock is used in an encapsulated semiconductor device and includes a neck and a shaped head integral with the neck. The mold lock can be formed to project above a support component, such as a heat spreader, of the semiconductor device and the neck is formed from the support component. The shaped head is of a greater dimension than the neck and can present a “T” shape in side view or a “Y” shape in side view. A base portion of the neck is seated within the support component. A method is provided for forming the described mold lock.
摘要翻译：提供了模具锁和形成模具锁的方法。模具锁用于封装的半导体器件中，并且包括与颈部成一体的颈部和形状的头部。模具锁可以形成为突出在半导体器件的支撑部件（例如散热器）上方，并且颈部由支撑部件形成。成形头部的尺寸比颈部大，并且可以在侧视图中呈现“T”形或侧视图中呈“Y”形。颈部的基部位于支撑部件内。提供了一种用于形成所述模具锁的方法。

3. 发明授权

US08058706B2 Delamination resistant packaged die having support and shaped die having protruding lip on support 有权
标题翻译：具有支撑和成形模具的耐层压包装模具在支撑件上具有突出的唇缘
公开(公告)号：US08058706B2
公开(公告)日：2011-11-15
申请号：US12555646
申请日：2009-09-08
申请人： Chien-Te Feng , Kazuaki Ano , Frank Yu , Trevor Liu
发明人： Chien-Te Feng , Kazuaki Ano , Frank Yu , Trevor Liu
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L23/13 , H01L23/3107 , H01L23/3128 , H01L23/49503 , H01L23/49513 , H01L23/49816 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2224/29035 , H01L2224/29101 , H01L2224/2919 , H01L2224/32014 , H01L2224/32105 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48475 , H01L2224/4848 , H01L2224/73265 , H01L2224/83192 , H01L2224/83194 , H01L2224/8385 , H01L2224/85051 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10156 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H01L2924/15151 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/19041 , H01L2924/35121 , Y10T29/49128 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599
摘要： A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites.
摘要翻译：封装的电子器件包括厚度形状的IC管芯，其包括顶部，顶面，有源电路，底部和底面。底面的横截面积比顶面的截面积小5％以提供具有底唇表面的突出唇缘。封装衬底包括顶部衬底表面，其包括衬底结合部位，底部衬底表面以及具有间隙区域的顶部衬底表面上的管芯支撑结构。 IC芯片的底部唇表面固定到模具支撑结构，并且IC芯片的底表面在模具支撑结构的下方延伸到间隙区域中。耦合连接器将IC芯片上的结合特征耦合到基板结合位置。

4. 发明授权

US08039955B2 Mold lock on heat spreader 有权
标题翻译：模具锁上散热器
公开(公告)号：US08039955B2
公开(公告)日：2011-10-18
申请号：US12463729
申请日：2009-05-11
申请人： Chien-Te Feng , Frank Yu
发明人： Chien-Te Feng , Frank Yu
IPC分类号： H01L23/48
CPC分类号： H01L23/3107 , H01L21/4878 , H01L23/3142 , H01L23/4334 , H01L23/562 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A mold lock and a method of forming the mold lock are provided. The mold lock is used in an encapsulated semiconductor device and includes a neck and a shaped head integral with the neck. The mold lock can be formed to project above a support component, such as a heat spreader, of the semiconductor device and the neck is formed from the support component. The shaped head is of a greater dimension than the neck and can present a “T” shape in side view or a “Y” shape in side view. A base portion of the neck is seated within the support component. A method is provided for forming the described mold lock.
摘要翻译：提供了模具锁和形成模具锁的方法。模具锁用于封装的半导体器件中，并且包括与颈部成一体的颈部和形状的头部。模具锁可以形成为突出在半导体器件的支撑部件（例如散热器）上方，并且颈部由支撑部件形成。成形头部的尺寸比颈部大，并且可以在侧视图中呈现“T”形或侧视图中呈“Y”形。颈部的基部位于支撑部件内。提供了一种用于形成所述模具锁的方法。

5. 发明授权

US08452912B2 Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read 有权
标题翻译：闪存系统具有增强的智能存储交换机和打包的元数据缓存，用于通过延迟和合并写入来缓解写入，直到主机读取
公开(公告)号：US08452912B2
公开(公告)日：2013-05-28
申请号：US12576216
申请日：2009-10-08
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/1036 , G06F2212/214 , G06F2212/7203 , G06F2212/7207 , G11C13/0004 , G11C16/102 , G11C19/0808 , G11C2211/5641 , G11C2216/30
摘要： A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
摘要翻译：闪存固态驱动器（SSD）具有智能存储交换机，可以减少写入快速写入的速度，而写入速度会比从主机接收到的更多的数据写入闪存。页面映射而不是块映射减少写入加速。主机命令加载到逻辑块地址（LBA）范围FIFO中。当新命令与FIFO中的旧命令重叠时，条目被分割，部分无效。主机数据与页边界对齐，前后获取的数据填充到边界。通过存储在元模式闪存块的元模式高速缓存中的元模式条目中的压缩元数据代码来检测和编码重复的数据模式。扇区数据未写入闪存。使用元数据映射表定位元模式条目。存储主机CRC用于与传入主机数据进行比较可以检测可跳过的相同数据写入，避免写入闪存。

6. 发明申请

US20120199285A1 MIXING BONDING ADHESIVE AT DIE BONDER BEFORE DISPENSE 有权
标题翻译：混合胶粘剂在配方之前
公开(公告)号：US20120199285A1
公开(公告)日：2012-08-09
申请号：US13020311
申请日：2011-02-03
申请人： Frank Yu , Eric Hsieh , Kevin Jin
发明人： Frank Yu , Eric Hsieh , Kevin Jin
IPC分类号： B32B7/12 , B29C47/36
CPC分类号： B05C11/10 , B29C47/0009 , B29C47/026
摘要： A method for die bonding includes positioning a dispenser in a die bonding apparatus, wherein the dispenser includes a reservoir having bonding adhesive therein including particles and a liquid carrier. The dispenser is moved to provide mechanical agitation to the dispenser for mixing the bonding adhesive into a homogeneous mixture of particles and the liquid carrier, wherein the bonding adhesive is not dispensed during moving. After the moving, the bonding adhesive is dispensed onto a bonding location on the workpiece without removing the dispenser from the die attach apparatus. An integrated circuit (IC) die is attached onto the bonding adhesive over the bonding location. The method can also include determining an amount of time elapsed after the last mixing of the bonding adhesive or the positioning of the dispenser in the die bonding apparatus, and automatically initiating movement for mixing only if the elapsed time exceeds a predetermined time.
摘要翻译：一种用于芯片接合的方法包括将分配器定位在芯片接合装置中，其中分配器包括其中具有粘合剂的储存器，其中包括颗粒和液体载体。移动分配器以向分配器提供机械搅拌，用于将粘合粘合剂混合成粒子和液体载体的均匀混合物，其中粘合粘合剂在移动期间不分配。在移动之后，将粘合粘合剂分配到工件上的粘合位置上，而不从管芯附接装置移除分配器。集成电路（IC）管芯在接合位置附着在粘结粘合剂上。该方法还可以包括确定在粘合粘合剂的最后混合之后经过的时间量或分散器在芯片粘合装置中的定位，以及仅在经过时间超过预定时间时才自动启动混合运动。

7. 发明授权

US08176238B2 Command queuing smart storage transfer manager for striping data to raw-NAND flash modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据分配到原始NAND闪存模块
公开(公告)号：US08176238B2
公开(公告)日：2012-05-08
申请号：US13104257
申请日：2011-05-10
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0607 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

8. 发明授权

US07707354B2 SRAM cache and flash micro-controller with differential packet interface 失效
标题翻译：具有差分数据包接口的SRAM缓存和闪存微控制器
公开(公告)号：US07707354B2
公开(公告)日：2010-04-27
申请号：US11876251
申请日：2007-10-22
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/2022 , G06F2212/2515
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导完成后，SRAM缓冲区还可以作为闪存数据缓存。缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。帧，分组和编码时钟处理也由串行接口执行。

9. 发明申请

US20100027329A1 Synchronous Page-Mode Phase-Change Memory with ECC and RAM Cache 失效
标题翻译：具有ECC和RAM缓存的同步页模式相变存储器
公开(公告)号：US20100027329A1
公开(公告)日：2010-02-04
申请号：US12579695
申请日：2009-10-15
申请人： Charles C. Lee , Frank Yu , David Q. Chow
发明人： Charles C. Lee , Frank Yu , David Q. Chow
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： G11C8/08 , G11C8/06 , G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2013/0085 , G11C2213/79
摘要： Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
摘要翻译：相变存储器（PCM）单元使用高电阻非晶和低电阻晶体状态的合金电阻存储数据。存储单元的设定电流脉冲的时间可以是100 ns，比读取或复位时间长得多。因此，写入时间取决于写入数据并且相对较长。页面模式缓存PCM设备具有高速缓存写入数据的查找表（LUT），该数据稍后被写入PCM存储体阵列。主机数据被锁存到行FIFO中并写入LUT中，从而将写入延迟减少到相对较慢的PCM。主机读取数据可由LUT提供或从PCM存储区中提取。 PCM组和LUT之间的多行页面缓冲区允许使用LUT进行更大的块传输。对LUT中的数据执行纠错码（ECC）检查和生成，将ECC数据写入PCM存储体中隐藏ECC延迟。

10. 发明申请

US20080320214A1 Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices 有权
标题翻译：具有智能存储传输管理器的多级控制器，用于交错多个单片闪存器件
公开(公告)号：US20080320214A1
公开(公告)日：2008-12-25
申请号：US12186471
申请日：2008-08-05
申请人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
发明人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0664 , G06F3/0688 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211 , G11C13/0004
摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.
摘要翻译：固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

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