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1. 发明授权

US06472743B2 Semiconductor package with heat dissipating structure 有权
标题翻译：具有散热结构的半导体封装
公开(公告)号：US06472743B2
公开(公告)日：2002-10-29
申请号：US09973151
申请日：2001-10-09
申请人： Chien-Ping Huang , Chi-Chuan Wu , Jui-Yu Chuang , Lien-Chih Chan , Ming-Chih Hsieh
发明人： Chien-Ping Huang , Chi-Chuan Wu , Jui-Yu Chuang , Lien-Chih Chan , Ming-Chih Hsieh
IPC分类号： H01L2334
CPC分类号： H01L23/4334 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45144 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01079 , H01L2924/07802 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor package with a heat dissipating structure is proposed, in which the heat dissipating structure is precisely positioned on a substrate, in a manner that a plurality of solder balls self-align with ball pads formed on the substrate, and support a heat sink to be positioned above a semiconductor chip mounted on the substrate. This therefore makes the heat sink closely abut a molding cavity of an encapsulating mold in a molding process, and prevents resin flash from occurring on the heat sink, so that a surface of the heat sink can be directly exposed to the atmosphere for improving heat dissipating efficiency. Moreover, the solder balls characterized in softness deform in response to a pressure generated by the encapsulating mold during molding. Therefore, the substrate can be protected from being damaged by the pressure, and thus quality of the semiconductor package can be assured.
摘要翻译：提出了一种具有散热结构的半导体封装，其中散热结构精确地定位在基板上，使得多个焊球与衬底上形成的球垫自对准，并且支撑散热器位于安装在基板上的半导体芯片的上方。因此，在成型工序中，散热片紧密地邻接封装模具的模腔，并且防止散热片上发生树脂闪光，使得散热片的表面可以直接暴露于大气中以改善散热效率。此外，柔软的焊料球响应于在模制期间由封装模具产生的压力而变形。因此，可以防止基板受到压力的损害，从而可以确保半导体封装的质量。

2. 发明授权

US06538321B2 Heat sink with collapse structure and semiconductor package with heat sink 有权
公开(公告)号：US06538321B2
公开(公告)日：2003-03-25
申请号：US09946999
申请日：2001-09-05
申请人： Chien-Ping Huang , Chi-Chuan Wu , Jui-Yu Chuang , Lien-Chi Chan
发明人： Chien-Ping Huang , Chi-Chuan Wu , Jui-Yu Chuang , Lien-Chi Chan
IPC分类号： H01L2310
CPC分类号： H01L23/4334 , H01L21/565 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00015 , H01L2924/00 , H01L2224/0401 , H01L2924/00012
摘要： A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.

3. 发明授权

US06858931B2 Heat sink with collapse structure for semiconductor package 有权
标题翻译：用于半导体封装的散热器具有塌陷结构
公开(公告)号：US06858931B2
公开(公告)日：2005-02-22
申请号：US10329093
申请日：2002-12-23
申请人： Chien-Ping Huang , Chi-Chuan Wu , Jui-Yu Chuang , Lien-Chi Chan
发明人： Chien-Ping Huang , Chi-Chuan Wu , Jui-Yu Chuang , Lien-Chi Chan
IPC分类号： H01L21/56 , H01L23/31 , H01L23/433 , H01L23/10 , H01L23/34
CPC分类号： H01L23/4334 , H01L21/565 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00015 , H01L2924/00 , H01L2224/0401 , H01L2924/00012
摘要： A heat sink with a collapse structure and a semiconductor device with the heat sink are proposed, in which the heat sink is in ladder-like shape due to a height difference formed between an extending portion and an body of the heat sink, and the body has at least one surface exposed to outside of the semiconductor package. The extending portion produces collapse deformation in response to stress from engagement of molds in a molding process, so as to prevent a semiconductor chip from being damaged by the stress. The heat sink directly attached to the chip allows heat generated by the chip to pass through the extending portion to the body of the heat sink, and then the heat can be dissipated through the exposed surface of the body to the outside of the semiconductor package, so as to improve the heat dissipating efficiency.
摘要翻译：提出了具有塌陷结构的散热器和具有散热器的半导体器件，其中散热器由于散热器的延伸部分和主体之间形成的高度差而呈阶梯状，并且主体具有暴露于半导体封装外部的至少一个表面。延伸部分在模制过程中响应于模具接合的应力而产生塌陷变形，以防止半导体芯片被应力损坏。直接连接到芯片的散热片允许由芯片产生的热量穿过延伸部分到达散热体的主体，然后可以将热量通过主体的暴露表面散发到半导体封装的外部，从而提高散热效率。

4. 发明授权

US06673690B2 Method of mounting a passive component over an integrated circuit package substrate 有权
标题翻译：将无源部件安装在集成电路封装基板上的方法
公开(公告)号：US06673690B2
公开(公告)日：2004-01-06
申请号：US09560031
申请日：2000-04-27
申请人： Jui Yu Chuang , Chi-Chuan Wu
发明人： Jui Yu Chuang , Chi-Chuan Wu
IPC分类号： H01L2120
CPC分类号： H05K3/305 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H05K3/1216 , H05K3/28 , H05K3/3452 , H05K2201/099 , H05K2201/10636 , H05K2201/10977 , H05K2203/0126 , H05K2203/0588 , Y02P70/611 , Y02P70/613 , H01L2924/00012 , H01L2924/00014
摘要： A method is proposed for mounting a passive component, such as a resistor or a capacitor, over an IC package substrate, such as a BGA (Ball Grid Array) substrate. Conventionally, the mounting of a passive component over a substrate would result in the undesired existence of a gap between the passive component and the substrate, which could lead to such problems as bridged short-circuit, popcorn effect, and dismounting of the passive component during subsequent processes. As a solution to these problems, the proposed method utilizes an electrically-insulative material, such as epoxy resin, to fill up the gap between the passive component and the substrate. Various techniques can be employed to fill the electrically-insulative material into the gap, including dispensing and stencil printing. Due to the fact that the proposed method allows no gap to be left between the passive component and the substrate, it can help eliminate the drawbacks of the prior art, thus allowing the manufactured IC package to be more assured in quality and more reliable to use.
摘要翻译：提出了一种将诸如电阻器或电容器的无源部件安装在诸如BGA（球栅阵列）基板的IC封装基板上的方法。通常，将无源部件安装在衬底上将导致无源部件和衬底之间的间隙的不期望的存在，这可能导致诸如桥接短路，爆米花效应和被动部件的拆卸之类的问题后续流程。作为这些问题的解决方案，所提出的方法利用诸如环氧树脂之类的电绝缘材料填充无源部件和基板之间的间隙。可以采用各种技术来将电绝缘材料填充到间隙中，包括分配和模版印刷。由于所提出的方法不会在无源部件和基板之间留下间隙，因此可以有助于消除现有技术的缺陷，从而允许制造的IC封装在质量上更加可靠并且更可靠地使用。

5. 发明申请

US20070284710A1 Method for fabricating flip-chip semiconductor package with lead frame as chip carrier 有权
标题翻译：制造具有引线框架作为芯片载体的倒装芯片半导体封装的方法
公开(公告)号：US20070284710A1
公开(公告)日：2007-12-13
申请号：US11891926
申请日：2007-08-14
申请人： Chi-Chuan Wu , Chien-Ping Huang , Han-Ping Pu
发明人： Chi-Chuan Wu , Chien-Ping Huang , Han-Ping Pu
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L24/16 , H01L23/4951 , H01L23/49558 , H01L23/49575 , H01L2224/13099 , H01L2224/16245 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/351 , H01L2924/00
摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.
摘要翻译：提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

6. 发明授权

US06555902B2 Multiple stacked-chip packaging structure 有权
公开(公告)号：US06555902B2
公开(公告)日：2003-04-29
申请号：US09895553
申请日：2001-06-28
申请人： Randy H. Y. Lo , Chien-Ping Huang , Chi-Chuan Wu
发明人： Randy H. Y. Lo , Chien-Ping Huang , Chi-Chuan Wu
IPC分类号： H01L2302
CPC分类号： H01L25/0652 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48137 , H01L2224/48145 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2924/14 , H01L2924/15311 , H01L2224/48227 , H01L2924/00012 , H01L2924/00
摘要： A packaging structure comprises a substrate, a plurality of semiconductor chips contiguously mounted into a plurality of stacked semiconductor chip sets, a plurality of supporting members, a plurality of adhesive layers, a plurality of wires and a molding compound. Each of the semiconductor chip sets comprises at least a semiconductor chip, each semiconductor chip having plurality of bonding pads. The size deviation between the semiconductor chip sets is less than 0.3 mm. The supporting members separate from one another the semiconductor chip sets stacked above the substrate. The adhesive layers bond the substrate, the supporting members and the semiconductor chips to one another. The wires connect the semiconductor chips to one another and to the substrate. The molding compound encapsulates the substrate, the semiconductor chips, the supporting members, and the adhesive layers.

7. 发明授权

US06593662B1 Stacked-die package structure 有权
标题翻译：堆叠式封装结构
公开(公告)号：US06593662B1
公开(公告)日：2003-07-15
申请号：US09631343
申请日：2000-08-02
申请人： Han-Ping Pu , Randy H. Y. Lo , Tzong-Dar Her , Chien-Ping Huang , Cheng-Shiu Hsiao , Chi-Chuan Wu
发明人： Han-Ping Pu , Randy H. Y. Lo , Tzong-Dar Her , Chien-Ping Huang , Cheng-Shiu Hsiao , Chi-Chuan Wu
IPC分类号： H01L2348
CPC分类号： H01L24/33 , H01L23/4334 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/0657 , H01L2224/05554 , H01L2224/05599 , H01L2224/2919 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49175 , H01L2224/73265 , H01L2224/83194 , H01L2224/8385 , H01L2224/85399 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A stacked-die package structure comprises a carrier, dies, spacers, adhesive layers, conductive lines, a mold compound, and solder balls. The carrier has an upper surface and a back surface opposite to the upper surface. The dies substantially having the same sizes are stacked one by one on the upper surface of the carrier, and a number of bonding pads are located around each die. The spacers are located between two adjacent dies. Adhesive layers located between the spacers, the dies, and the carrier for adhering layers therebetween. The conducting lines are respectively electrically connected between each of the bonding pads of the dies and the carrier. And the mold compound is formed over the upper surface of the carrier, for encapsulating the spacers, the dies and the adhesive layers. A substrate with solder balls or a lead frame having pins is suitable for serving as the carrier.
摘要翻译：堆叠管芯封装结构包括载体，管芯，间隔物，粘合剂层，导电线，模具化合物和焊球。载体具有与上表面相对的上表面和后表面。基本上具有相同尺寸的模具在载体的上表面上一个接一个堆叠，并且多个焊盘位于每个管芯周围。间隔件位于两个相邻的模具之间。位于间隔件，模具和载体之间的粘合层，用于在其间粘合层。导体线分别电连接在管芯和载体的每个接合焊盘之间。并且模制化合物形成在载体的上表面上，用于封装间隔物，模具和粘合剂层。具有焊球或具有引脚的引线框架的基板适合用作载体。

8. 发明授权

US06590281B2 Crack-preventive semiconductor package 有权
标题翻译：防裂半导体封装
公开(公告)号：US06590281B2
公开(公告)日：2003-07-08
申请号：US10060564
申请日：2002-01-30
申请人： Chi-Chuan Wu , Chien-Ping Huang
发明人： Chi-Chuan Wu , Chien-Ping Huang
IPC分类号： H01L2334
CPC分类号： H01L24/33 , H01L23/3107 , H01L23/4334 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/06135 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/484 , H01L2224/48465 , H01L2224/48599 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2924/00014 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.
摘要翻译：提出了一种QFN半导体封装及其制造方法，其中采用具有多个引线的引线框架，并且每个引线的内端形成有突出部分。引线接合区域和突起附着区域分别限定在突出部分的相对表面上并且交错位置。这允许从引线接合器施加到引线接合区域的力不会不利地影响注入在凸块附接区域上的焊料凸起，使得焊料凸块可以在结构上确保而不会破裂。此外，可以防止与凸块附接区域间隔开的引线接合区域被焊料凸块注入中使用的蚀刻溶液污染，从而可以良好地保持引线接合质量。

9. 发明授权

US06281047B1 Method of singulating a batch of integrated circuit package units constructed on a single matrix base 失效
标题翻译：在单个矩阵基础上构建一批集成电路封装单元的方法
公开(公告)号：US06281047B1
公开(公告)日：2001-08-28
申请号：US09709224
申请日：2000-11-10
申请人： Chi-Chuan Wu , Chien-Ping Huang
发明人： Chi-Chuan Wu , Chien-Ping Huang
IPC分类号： H01L21301
CPC分类号： H01L23/3107 , H01L21/56 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05599 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012 , H01L2224/45099
摘要： A package singulation method is proposed, which is useful for the singulation of a combined batch of small-scale integrated circuit package units, such as TFBGA (Thin & Fine Ball Grid Array) or QFN (Quad Flat Non-leaded) package units, that are constructed together on a single matrix base, without leaving remnant portions of provisional bars, such as electroplating bars or connect bars, in the singulated package units. The proposed package singulation method is characterized in the use of a two-step cutting procedure, where a large-width cutting blade is used in the first cutting step to cut into just the matrix base but not into the encapsulation body so that the provisional electroplating bar or connect bar can be entirely cut away; and in the second cutting step, a small-width cutting blade is used to cut all the way through the encapsulation body to singulate individual package units. The use of the large-width cutting blade in the first cutting step ensures easy alignment so that the provisional electroplating bar or connect bar would be absolutely cut away; and the use of the small-width cutting blade in the second cutting step allows only a small part of the encapsulation body over the matrix base to be cut away, so that the overall circuit layout area of each package site can remain the same.
摘要翻译：提出了一种封装分割方法，可用于组合批量的小型集成电路封装单元，如TFBGA（Thin＆Fine Ball Grid Array）或QFN（Quad Flat Non-leaded）封装单元，在单个矩阵基体上一起构造，而不会在分离的封装单元中留下临时条的残余部分，例如电镀条或连接条。提出的包装分割方法的特征在于使用两步切割程序，其中在第一切割步骤中使用大宽度切割刀片切割成刚好的基质基底而不进入包封体，使得临时电镀酒吧或连接杆可以完全切除; 并且在第二切割步骤中，使用小宽度切割刀片将所有方式切割通过封装体以分割单个包装单元。在第一切割步骤中使用大宽度切割刀片确保容易对准，使得临时电镀棒或连接杆将被绝对切除; 并且在第二切割步骤中使用小宽度切割刀片仅允许将矩形基底上的小部分封装体切除，使得每个封装部位的整个电路布局区域可以保持相同。

10. 发明授权

US07781264B2 Method for fabricating flip-chip semiconductor package with lead frame as chip carrier 有权
标题翻译：制造具有引线框架作为芯片载体的倒装芯片半导体封装的方法
公开(公告)号：US07781264B2
公开(公告)日：2010-08-24
申请号：US11891926
申请日：2007-08-14
申请人： Chi-Chuan Wu , Chien-Ping Huang , Han-Ping Pu
发明人： Chi-Chuan Wu , Chien-Ping Huang , Han-Ping Pu
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L24/16 , H01L23/4951 , H01L23/49558 , H01L23/49575 , H01L2224/13099 , H01L2224/16245 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/351 , H01L2924/00
摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.
摘要翻译：提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

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