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1. 发明申请

US20130012012A1 SEMICONDUCTOR PROCESS 审中-公开
标题翻译：半导体工艺
公开(公告)号：US20130012012A1
公开(公告)日：2013-01-10
申请号：US13179558
申请日：2011-07-10
申请人： Chien-Liang Lin , Yu-Ren Wang , Ying-Wei Yen , Shao-Wei Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
发明人： Chien-Liang Lin , Yu-Ren Wang , Ying-Wei Yen , Shao-Wei Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
IPC分类号： H01L21/28
CPC分类号： H01L21/268 , H01L21/28194 , H01L21/28211 , H01L21/324 , H01L21/3247 , H01L29/51
摘要： A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.
摘要翻译：半导体工艺包括以下步骤。提供其上具有氧化物层的衬底。进行高于1000℃的高温处理，以在基板和氧化物层之间形成熔融层。进行去除处理以去除氧化物层和熔化层。

2. 发明申请

US20120306028A1 SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF 审中-公开
公开(公告)号：US20120306028A1
公开(公告)日：2012-12-06
申请号：US13118561
申请日：2011-05-30
申请人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen
发明人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.
摘要翻译：提供一种半导体工艺，包括：提供衬底，形成缓冲层，形成介电常数高的介电层，其中形成缓冲层的方法包括：（1）进行氧化处理; 进行烘烤处理; 或者，（2）进行氧化处理; 进行热氮化处理; 并进行等离子体氮化处理; 或者，（3）进行去耦等离子体氧化处理。此外，还提供了通过最后工艺制造的半导体结构。

3. 发明授权

US09000568B2 Semiconductor structure and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09000568B2
公开(公告)日：2015-04-07
申请号：US13244948
申请日：2011-09-26
申请人： Szu-Hao Lai , Yu-Ren Wang , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh , Te-Lin Sun
发明人： Szu-Hao Lai , Yu-Ren Wang , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh , Te-Lin Sun
IPC分类号： H01L29/51 , H01L21/28 , H01L29/66
CPC分类号： H01L21/28185 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.
摘要翻译：半导体结构包括基板，氧化物层，金属氧氮化物层和金属氧化物层。氧化物层位于衬底上。金属氮氧化物层位于氧化物层上。金属氧化物层位于金属氮氧化物层上。此外，本发明还提供了一种用于形成半导体结构的半导体工艺。

4. 发明申请

US20130075874A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130075874A1
公开(公告)日：2013-03-28
申请号：US13244948
申请日：2011-09-26
申请人： Szu-Hao Lai , Yu-Ren Wang , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh , Te-Lin Sun
发明人： Szu-Hao Lai , Yu-Ren Wang , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh , Te-Lin Sun
IPC分类号： H01L29/06 , H01L21/31
CPC分类号： H01L21/28185 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A semiconductor structure includes a substrate, an oxide layer, a metallic oxynitride layer and a metallic oxide layer. The oxide layer is located on the substrate. The metallic oxynitride layer is located on the oxide layer. The metallic oxide layer is located on the metallic oxynitride layer. In addition, the present invention also provides a semiconductor process for forming the semiconductor structure.
摘要翻译：半导体结构包括基板，氧化物层，金属氧氮化物层和金属氧化物层。氧化物层位于衬底上。金属氮氧化物层位于氧化物层上。金属氧化物层位于金属氮氧化物层上。此外，本发明还提供了一种用于形成半导体结构的半导体工艺。

5. 发明授权

US08551876B2 Manufacturing method for semiconductor device having metal gate 有权
标题翻译：具有金属栅极的半导体器件的制造方法
公开(公告)号：US08551876B2
公开(公告)日：2013-10-08
申请号：US13212187
申请日：2011-08-18
申请人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
发明人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/517 , H01L29/66545 , H01L29/7848
摘要： A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
摘要翻译：具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及对第一功函数金属层进行解耦等离子体氧化。

6. 发明申请

US20130045594A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE 有权
标题翻译：具有金属栅的半导体器件的制造方法
公开(公告)号：US20130045594A1
公开(公告)日：2013-02-21
申请号：US13212187
申请日：2011-08-18
申请人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
发明人： Yu-Ren Wang , Te-Lin Sun , Szu-Hao Lai , Po-Chun Chen , Chih-Hsun Lin , Che-Nan Tsai , Chun-Ling Lin , Chiu-Hsien Yeh
IPC分类号： H01L21/28
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/517 , H01L29/66545 , H01L29/7848
摘要： A manufacturing method for a semiconductor device having a metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.
摘要翻译：具有金属栅极的半导体器件的制造方法包括提供至少形成有第一半导体器件的衬底，在第一半导体器件中形成第一栅极沟槽，在第一栅极沟槽中形成第一功函数金属层，以及对第一功函数金属层进行解耦等离子体氧化。

7. 发明授权

US08691688B2 Method of manufacturing semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US08691688B2
公开(公告)日：2014-04-08
申请号：US13525568
申请日：2012-06-18
申请人： Hsin-Yu Chen , Yu-Han Tsai , Chun-Ling Lin , Ching-Li Yang , Home-Been Cheng
发明人： Hsin-Yu Chen , Yu-Han Tsai , Chun-Ling Lin , Ching-Li Yang , Home-Been Cheng
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.
摘要翻译：提供了一种处理衬底的方法。该方法包括：提供衬底，其中衬底包括硅层; 蚀刻基板以形成空腔; 在腔的一部分中填充第一导体; 对所述第一导体执行第一热处理; 在腔中填充第二导体以填充空腔; 以及对所述第一导体和所述第二导体执行第二热处理。

8. 发明授权

US07580194B2 Projection lens with high resolution and reduced overall length 失效
标题翻译：具有高分辨率和缩短整体长度的投影镜头
公开(公告)号：US07580194B2
公开(公告)日：2009-08-25
申请号：US11955291
申请日：2007-12-12
申请人： Chun-Ling Lin
发明人： Chun-Ling Lin
IPC分类号： G02B9/00
CPC分类号： G02B15/177
摘要： An exemplary projection lens includes, in this order from the screen-side thereof, a negative lens group having negative refraction of power, and a positive lens group having positive refraction of power. The positive and negative lens groups each include a number of positive and negative lenses. The focal length of the projection lens is adjustable. The projection lens satisfies the formulas of: −2 56, where F1, and F2 respectively represent the effective focal lengths of the negative lens group and the positive lens group, Fw is the shortest effective focal length of the projection lens, and Vg2 is the average of the Abbe numbers of the positive lenses in the positive lens group.
摘要翻译：示例性的投影透镜从其屏幕侧依次包括具有负折射率的负透镜组和具有正的折射率的正透镜组。正和负透镜组各自包括许多正和负透镜。投影镜头的焦距可调。投影透镜满足以下公式：-2 56，其中F1和F2分别表示负透镜组和正透镜组的有效焦距，Fw是投影透镜的最短有效焦距，Vg2是所述投影透镜的阿贝数的平均值阳性透镜在正透镜组中。

9. 发明申请

US20130337645A1 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20130337645A1
公开(公告)日：2013-12-19
申请号：US13525568
申请日：2012-06-18
申请人： Hsin-Yu Chen , Yu-Han Tsai , Chun-Ling Lin , Ching-Li Yang , Home-Been Cheng
发明人： Hsin-Yu Chen , Yu-Han Tsai , Chun-Ling Lin , Ching-Li Yang , Home-Been Cheng
IPC分类号： H01L21/768
CPC分类号： H01L21/76898
摘要： A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor.
摘要翻译：提供了一种处理衬底的方法。该方法包括：提供衬底，其中衬底包括硅层; 蚀刻基板以形成空腔; 在腔的一部分中填充第一导体; 对所述第一导体执行第一热处理; 在腔中填充第二导体以填充空腔; 以及对所述第一导体和所述第二导体执行第二热处理。

10. 发明申请

US20120305403A1 Electrical Chemical Plating Process 有权
标题翻译：电化学镀工艺
公开(公告)号：US20120305403A1
公开(公告)日：2012-12-06
申请号：US13154420
申请日：2011-06-06
申请人： Chun-Ling Lin , Yen-Liang Lu , Chi-Mao Hsu , Chin-Fu Lin , Chun-Hung Chen , Tsun-Min Cheng , Meng-Hong Tsai
发明人： Chun-Ling Lin , Yen-Liang Lu , Chi-Mao Hsu , Chin-Fu Lin , Chun-Hung Chen , Tsun-Min Cheng , Meng-Hong Tsai
IPC分类号： C25D7/12 , C25D5/00
CPC分类号： C25D5/54 , C25D3/38 , C25D5/00 , C25D5/10 , C25D7/123 , H01L21/2885 , H01L21/76879
摘要： An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.
摘要翻译：提供电化学镀工艺。半导体结构设置在电镀平台中。进行预电镀步骤，其中预电镀步骤在固定电压环境下进行，并且在电流高于电镀平台的阈值电流之后持续0.2至0.5秒。在预电镀步骤之后，对半导体结构进行第一电镀步骤。

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