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1. 发明授权

US07186662B2 Method for forming a hard mask for gate electrode patterning and corresponding device 有权
标题翻译：用于形成用于栅极电极图案化的硬掩模和相应装置的方法
公开(公告)号：US07186662B2
公开(公告)日：2007-03-06
申请号：US10964841
申请日：2004-10-13
申请人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
IPC分类号： H01L21/461
CPC分类号： H01L21/28123 , H01L21/0217 , H01L21/28035 , H01L21/31608 , H01L21/3185
摘要： A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.
摘要翻译：公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

2. 发明申请

US20060081917A1 Method for forming a hard mask for gate electrode patterning and corresponding device 有权
标题翻译：用于形成用于栅极电极图案化的硬掩模和相应装置的方法
公开(公告)号：US20060081917A1
公开(公告)日：2006-04-20
申请号：US10964841
申请日：2004-10-13
申请人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
IPC分类号： H01L29/76
CPC分类号： H01L21/28123 , H01L21/0217 , H01L21/28035 , H01L21/31608 , H01L21/3185
摘要： A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.
摘要翻译：公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

3. 发明授权

US08557669B2 MOSFET device with localized stressor 有权
标题翻译：具有局部应力源的MOSFET器件
公开(公告)号：US08557669B2
公开(公告)日：2013-10-15
申请号：US12176655
申请日：2008-07-21
申请人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Pang-Yen Tsai , Chie-Chien Chang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/42
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L29/165 , H01L29/45 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.
摘要翻译：提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。应力诱导层可以是凹陷区域或非凹陷区域。第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

4. 发明申请

US20080160709A1 Advanced activation approach for MOS devices 有权
标题翻译： MOS器件的高级激活方法
公开(公告)号：US20080160709A1
公开(公告)日：2008-07-03
申请号：US11648371
申请日：2006-12-29
申请人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
发明人： Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Keh-Chiang Ku , Chun-Feng Nieh , Li-Ting Wang , Hsun Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/324 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在栅极电介质上形成栅电极; 形成邻近所述栅极电介质和所述栅电极的源极/漏极区域; 在源极/漏极区域和栅极电极上形成吸收覆盖层; 通过向吸收覆盖层施加高能量光来进行激活; 并去除吸收层。

5. 发明申请

US20070284615A1 Ultra-shallow and highly activated source/drain extension formation using phosphorus 有权
标题翻译：使用磷的超浅和高活化的源/漏延伸形成
公开(公告)号：US20070284615A1
公开(公告)日：2007-12-13
申请号：US11521660
申请日：2006-09-15
申请人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
发明人： Keh-Chiang Ku , Chun-Feng Nieh , Li-Ping Huang , Chih-Chiang Wang , Chien-Hao Chen , Hsun Chang , Li-Ting Wang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/739
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0847 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.
摘要翻译：半导体器件包括在半导体衬底上的栅极堆叠，半导体衬底中的轻掺杂n型源极/漏极（LDD）区域并且邻近栅极堆叠，其中LDD区域包括n型杂质，重掺杂n- （N + S / D）区，其中N + S / D区包括n型杂质，半导体衬底中的非淀粉化注入（PAI）区，其中PAI 区域包括端部范围（EOR）区域和半导体衬底中的间隙阻挡区域，其中间隙阻挡区域的深度大于LDD区域的深度但小于EOR区域的深度。

6. 发明授权

US07157350B2 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
公开(公告)号：US07157350B2
公开(公告)日：2007-01-02
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

7. 发明申请

US20060286758A1 Super anneal for process induced strain modulation 有权
公开(公告)号：US20060286758A1
公开(公告)日：2006-12-21
申请号：US11199011
申请日：2005-08-08
申请人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/7624 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

8. 发明申请

US20060125028A1 MOSFET device with localized stressor 有权
标题翻译：具有局部应力源的MOSFET器件
公开(公告)号：US20060125028A1
公开(公告)日：2006-06-15
申请号：US11012413
申请日：2004-12-15
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.
摘要翻译：提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源/漏区的晶体管，在栅电极和源/漏区上形成高应力膜，然后除去高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。接触蚀刻停止层可以形成在晶体管上。

9. 发明申请

US20050253194A1 SOI-like structure in a bulk semiconductor substrate and method of forming same 有权
标题翻译：体半导体衬底中的SOI类结构及其形成方法
公开(公告)号：US20050253194A1
公开(公告)日：2005-11-17
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/324 , H01L21/762 , H01L27/01 , H01L27/12
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

10. 发明申请

US20050159008A1 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US20050159008A1
公开(公告)日：2005-07-21
申请号：US10758317
申请日：2004-01-15
申请人： Vincent Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/311 , H01L21/314 , H01L21/3213 , H01L21/336 , H01L21/477 , H01L29/51
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

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