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1. 发明申请

US20070037328A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20070037328A1
公开(公告)日：2007-02-15
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

2. 发明授权

US07977227B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07977227B2
公开(公告)日：2011-07-12
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

3. 发明授权

US07468299B2 Non-volatile memory cells and methods of manufacturing the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US07468299B2
公开(公告)日：2008-12-23
申请号：US11197659
申请日：2005-08-04
申请人： ChiaHua Ho , Erh-Kun Lai , Hang-Ting Lue
发明人： ChiaHua Ho , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.
摘要翻译：用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

4. 发明授权

US07414282B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07414282B2
公开(公告)日：2008-08-19
申请号：US11203087
申请日：2005-08-15
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

5. 发明申请

US20090075466A1 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090075466A1
公开(公告)日：2009-03-19
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

6. 发明申请

US20070201276A1 Dual-gate, non-volatile memory cells, arrays thereof, methods of manufacturing the same and methods of operating the same 有权
标题翻译：双栅极，非易失性存储单元，其阵列，其制造方法及其操作方法
公开(公告)号：US20070201276A1
公开(公告)日：2007-08-30
申请号：US11352788
申请日：2006-02-13
申请人： ChiaHua Ho , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Kuang Hsieh
发明人： ChiaHua Ho , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Kuang Hsieh
IPC分类号： G11C16/04 , H01L21/336 , G11C11/34 , H01L29/788
CPC分类号： H01L29/7923 , G11C16/0475 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/66833
摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.
摘要翻译：存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

7. 发明申请

US20070031999A1 Non-volatile memory cells and methods of manufacturing the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US20070031999A1
公开(公告)日：2007-02-08
申请号：US11197659
申请日：2005-08-04
申请人： ChiaHua Ho , Erh-Kun Lai , Hang-Ting Lue
发明人： ChiaHua Ho , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.
摘要翻译：用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

8. 发明授权

US08482052B2 Silicon on insulator and thin film transistor bandgap engineered split gate memory 有权
标题翻译：硅绝缘体和薄膜晶体管带隙设计的分离栅极存储器
公开(公告)号：US08482052B2
公开(公告)日：2013-07-09
申请号：US12056489
申请日：2008-03-27
申请人： Hang-Ting Lue , Erh-Kun Lai
发明人： Hang-Ting Lue , Erh-Kun Lai
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L29/66833 , G11C16/0466 , G11C16/0483 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11551 , H01L27/11568 , H01L27/11578 , H01L29/792
摘要： Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.
摘要翻译：薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。

9. 发明授权

US08324681B2 Stacked non-volatile memory device and methods for fabricating the same 有权
标题翻译：堆叠的非易失性存储器件及其制造方法
公开(公告)号：US08324681B2
公开(公告)日：2012-12-04
申请号：US13162386
申请日：2011-06-16
申请人： Erh-Kun Lai , Hang-Ting Lue , Kuang Yeu Hsieh
发明人： Erh-Kun Lai , Hang-Ting Lue , Kuang Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/792
摘要： A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.
摘要翻译：堆叠的非易失性存储器件包括堆叠在彼此顶部的多个位线和字线层。位线层包括多个位线，其可以使用先进的处理技术形成，从而使器件的制造成本高效且成本有效。该器件可以配置为NAND操作。

10. 发明申请

US20120220111A1 INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN 审中-公开
标题翻译：注射方法与肖特源/排水
公开(公告)号：US20120220111A1
公开(公告)日：2012-08-30
申请号：US13463264
申请日：2012-05-03
申请人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
发明人： Yi-Hsuan Hsiao , Erh-Kun Lai , Hang-Ting Lue
IPC分类号： H01L21/04
CPC分类号： H01L29/665 , G11C16/0408 , H01L29/40117 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.
摘要翻译：描述了具有肖特基源和漏极的非易失性存储单元的注入方法。载流子注入效率由硅化物和硅的界面特性控制。通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。

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