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1. 发明授权

US06724036B1 Stacked-gate flash memory cell with folding gate and increased coupling ratio 有权
标题翻译：具有折叠浮动栅极的叠栅式闪存单元和增加的耦合比
公开(公告)号：US06724036B1
公开(公告)日：2004-04-20
申请号：US09654776
申请日：2000-09-05
申请人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
发明人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： A stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling is described. An unconventionally high isolation oxide layer is formed in a shallow trench isolation (STI) in a substrate. The deep opening in the space between the STIs is conformally lined with a polysilicon to form a floating gate extending above the opening. A conformal intergate oxide lines the entire floating gate. A layer of polysilicon overlays the intergate oxide and protrudes downward into the openings to form a control gate with increased coupling to the floating gate.
摘要翻译：描述了具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极闪存单元。在衬底中的浅沟槽隔离（STI）中形成非常规的高隔离氧化层。在STI之间的空间中的深开口共形地衬有多晶硅以形成在开口上方延伸的浮动栅极。保形隔离层氧化物对整个浮动栅线进行排列。一层多晶硅覆盖了间隔栅极氧化物并向下突出到开口中，以形成一个与浮动栅极增加耦合的控制栅极。

2. 发明授权

US6153494A Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash 有权
标题翻译：通过堆叠栅极闪存中的横向耦合来增加字线与浮动栅极的耦合比的方法
公开(公告)号：US6153494A
公开(公告)日：2000-11-28
申请号：US310257
申请日：1999-05-12
申请人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
发明人： Chia-Ta Hsieh , Di-Son Kuo , Yai-Fen Lin , Chrong Jung Lin , Jong Chen , Hung-Der Su
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) through the nitride layer into the substrate, filling the STI with isolation oxide, removing the nitride thus leaving behind a deep opening about the filled STI, filling conformally the opening with a first polysilicon layer to form a floating gate, forming interpoly oxide layer over the floating gate, and then forming a second polysilicon layer to form the control gate and finally forming the self-aligned source of the stacked-gate flash memory cell of the invention. A stacked-gate flash memory cell is also provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.
摘要翻译：提供一种用于形成具有高阶氧化物和高横向耦合的浅沟槽隔离的堆叠栅极快闪存储器单元的方法。这是通过首先沉积非常规高或较厚的氮化物层，然后通过氮化物层形成浅沟槽隔离（STI）到衬底中，用隔离氧化物填充STI，从而除去氮化物，从而留下围绕填充STI，用第一多晶硅层保形地填充开口以形成浮置栅极，在浮置栅极上形成多晶硅层，然后形成第二多晶硅层以形成控制栅极，并最终形成堆叠的自对准源本发明的闪存单元。还提供了堆叠栅极闪存单元，其具有具有高阶氧化物和高横向耦合的浅沟槽隔离。

3. 发明授权

US6127227A Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory 有权
标题翻译：闪存中通过N2处理对ONO厚度进行薄膜控制和逐步门极氧化抑制
公开(公告)号：US6127227A
公开(公告)日：2000-10-03
申请号：US236491
申请日：1999-01-25
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8247
CPC分类号： H01L21/28211 , H01L21/28273 , H01L29/511
摘要： A method of forming a flash memory cell is disclosed where nitrogen treatment or implantation is employed. Nitrogen introduced into the upper layers of the polysilicon of the floating gate is instrumental in forming an unusually thin layer comprising nitrogen-oxygen-silicon. This N--O--Si layer is formed while growing the bottom oxide layer of the oxide-nitride-oxide, or ONO, the intergate layer between the floating gate and the control gate of the flash memory cell. Nitrogen in the first polysilicon layer provides control for the thickness of the bottom oxide while at the same time suppressing the gradual gate oxidation (GGO) effect in the floating gate. The now augmented ONO composite through the N--O--Si layer provides an enhanced intergate dielectric and hence, a flash memory cell with more precise coupling ratio and better performance.
摘要翻译：公开了一种形成闪存单元的方法，其中采用氮气处理或植入。引入浮栅的多晶硅的上层的氮有助于形成包含氮 - 氧 - 硅的异常薄的层。在生长氧化物 - 氮化物 - 氧化物的底部氧化物层（ONO）的同时，在浮动栅极和闪存单元的控制栅极之间形成栅极层，形成N-O-Si层。第一多晶硅层中的氮提供对底部氧化物的厚度的控制，同时抑制浮动栅极中的逐渐栅极氧化（GGO）效应。现在通过N-O-Si层增强的ONO复合材料提供增强的隔间电介质，因此提供具有更精确的耦合比和更好性能的闪存单元。

4. 发明授权

US06495880B2 Method to fabricate a flash memory cell with a planar stacked gate 有权
标题翻译：用平面堆叠栅极制造闪存单元的方法
公开(公告)号：US06495880B2
公开(公告)日：2002-12-17
申请号：US09760309
申请日：2001-01-16
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L29/66825
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.
摘要翻译：描述了一种制造具有改进的堆叠栅极拓扑的堆叠栅极闪存EEPROM器件的新方法。在半导体衬底上形成隔离区。隧道氧化物层设置在半导体衬底的表面上。沉积在隧道氧化物层上的第一多晶硅层。将第一多晶硅层抛光直到多晶硅的顶表面平坦并平行于半导体衬底的顶表面。蚀刻掉第一多晶硅层以形成浮栅。源极和漏极区域形成在半导体衬底内。沉积在第一多晶硅层上的多层介电层。第二多晶硅层沉积在叠层电介质层上。蚀刻掉第二多晶硅层和互聚电介质层以形成覆盖浮栅的控制栅极。绝缘层沉积在氧化层和控制栅上。通过绝缘层到底层的控制栅极和底层的源极和漏极区域形成接触开口。接触开口填充有导电层以完成闪速EEPROM装置的制造。

5. 发明授权

US6074915A Method of making embedded flash memory with salicide and sac structure 有权
标题翻译：制造具有自杀和囊结构的嵌入式闪存的方法
公开(公告)号：US6074915A
公开(公告)日：2000-06-13
申请号：US135044
申请日：1998-08-17
申请人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
发明人： Jong Chen , Chrong Jung Lin , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L21/8247
CPC分类号： H01L27/11526 , H01L27/11536
摘要： A combined method of fabricating embedded flash memory cells having salicide and self-aligned contact (SAC) structures is disclosed. The SAC structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask. This is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits. Thus, the etching of the self-aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed. Furthermore, the thin and thick portions of the dual-gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate.
摘要翻译：公开了一种制造具有自对准接触（SAC）结构的嵌入式闪存单元的组合方法。半导体器件的周边区域的单元区域和硅化物触点的SAC结构使用单个掩模形成。这是通过明确的形成和去除包括存储单元中的掺杂的第一和第二多晶硅层以及在外围电路中使用的本征多晶硅层的各种层的顺序来实现的。因此，存储单元的自对准接触孔的蚀刻同时实现了周边区域的浸渍接触孔。此外，两个区域的双栅极氧化物的薄而厚的部分形成为总工艺的天然部分，而不必诉诸于栅极氧化物层的一部分的光致抗蚀剂掩模以及伴随的污染问题，同时去除栅极氧化物在衬底的另一区域中的部分。

6. 发明授权

US06190969B1 Method to fabricate a flash memory cell with a planar stacked gate 有权
公开(公告)号：US06190969B1
公开(公告)日：2001-02-20
申请号：US09257722
申请日：1999-02-25
申请人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
发明人： Chrong Jung Lin , Jong Chen , Hung-Der Su , Di-Son Kuo
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L29/66825
摘要： A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate. Contact openings are formed through the insulating layer to the underlying control gate and to the underlying source and drain regions. The contact openings are filled with a conducting layer to complete the fabrication of the Flash EEPROM device.

7. 发明授权

US06465836B2 Vertical split gate field effect transistor (FET) device 有权
标题翻译：垂直分流栅场效应晶体管（FET）器件
公开(公告)号：US06465836B2
公开(公告)日：2002-10-15
申请号：US09821199
申请日：2001-03-29
申请人： Chrong Jung Lin , Sheng-Wei Tsao , Di-Son Kuo , Jack Yeh , Wen-Ting Chu , Chung-Li Chang , Chia-Ta Hsieh
发明人： Chrong Jung Lin , Sheng-Wei Tsao , Di-Son Kuo , Jack Yeh , Wen-Ting Chu , Chung-Li Chang , Chia-Ta Hsieh
IPC分类号： H01L29788
CPC分类号： H01L29/7887 , H01L29/42336
摘要： Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transistor (FET) device. Similarly, there is also formed within the split gate field effect transistor a floating gate electrode within the trench and covering within the trench a lower sub-portion of the channel region. Finally, the floating gate electrode in turn has formed vertically and horizontally overlapping thereover within the trench a control gate electrode which covers an upper sub-portion of the channel. The split gate field effect transistor (FET) device is fabricated with enhanced areal density and enhanced performance.
摘要翻译：在分裂栅场效应晶体管（FET）器件和用于制造分离栅场效应晶体管（FET）器件的方法中，在半导体衬底内形成沟槽，其沟槽内的沟槽区域完全包含在分离栅极场内效应晶体管（FET）器件。类似地，在分裂栅极场效应晶体管内还形成有沟槽内的浮置栅电极，并且在沟槽内覆盖沟道区的下部子部分。最后，浮栅电极依次形成在沟槽内垂直和水平重叠的覆盖通道的上部子部分的控制栅电极。分离栅场效应晶体管（FET）器件制造具有增强的面密度和增强的性能。

8. 发明授权

US06326662B1 Split gate flash memory device with source line 有权
标题翻译：分流闸闪存器件与源极线
公开(公告)号：US06326662B1
公开(公告)日：2001-12-04
申请号：US09633643
申请日：2000-08-07
申请人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。栅电极中心的图案源极线槽向下堆叠到衬底。在源线插槽的底部形成源区。在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。形成自对准漏极区。

9. 发明授权

US06297099B1 Method to free control tunneling oxide thickness on poly tip of flash 有权
标题翻译：自由控制闪光多头尖端的隧道氧化物厚度的方法
公开(公告)号：US06297099B1
公开(公告)日：2001-10-02
申请号：US09765045
申请日：2001-01-19
申请人： Chia-Ta Hsieh , Di-Son Kuo , Jack Yeh , Chrong Jung Lin , Wen-Ting Chu , Chung-Li Chang
发明人： Chia-Ta Hsieh , Di-Son Kuo , Jack Yeh , Chrong Jung Lin , Wen-Ting Chu , Chung-Li Chang
IPC分类号： H01L218247
CPC分类号： H01L21/28273 , H01L29/42324 , Y10S438/981
摘要： A method of fabricating a floating gate/word line device, comprising the following steps. A semiconductor structure is provided. A floating gate portion is formed over the semiconductor structure. The floating gate portion having side walls and a top surface. A poly-oxide portion is formed over the top surface of the floating gate. An interpoly oxide layer is formed over the semiconductor structure, the poly-oxide portion and the poly-oxide portion. The interpoly oxide layer having an initial thickness and includes: a word line region portion over at least a portion of the semiconductor structure adjacent the floating gate portion; side wall area portions over the floating gate portion side walls; and a top portion over the poly-oxide portion. The initial thickness of the top portion of the interpoly oxide layer is reduced to a second thickness without reducing the initial thickness of the interpoly oxide word line region portion or an appreciable portion of the interpoly oxide side wall area portion. A polysilicon layer is formed over the interpoly oxide layer. The structure is patterned to form a floating gate/word line device.
摘要翻译：一种制造浮栅/字线装置的方法，包括以下步骤。提供半导体结构。在半导体结构上方形成浮栅部分。浮动门部分具有侧壁和顶面。多晶氧化物部分形成在浮动栅极的顶表面上。在半导体结构，多晶氧化物部分和多晶氧化物部分之上形成多层氧化物层。所述多晶硅氧化物层具有初始厚度，并且包括：与所述浮动栅极部分相邻的所述半导体结构的至少一部分上的字线区域部分; 浮动部分侧壁上的侧壁区域部分; 以及多个氧化物部分上方的顶部。互折层氧化物层的顶部的初始厚度减小到第二厚度，而不会减小多晶氧化物字线区域部分的初始厚度或多余氧化物侧壁区域部分的明显部分。在多晶硅层上形成多晶硅层。将结构图案化以形成浮动栅/字线装置。

10. 发明授权

US6133097A Method for forming mirror image split gate flash memory devices by forming a central source line slot 有权
标题翻译：通过形成中心源线槽来形成镜像分离门闪存器件的方法
公开(公告)号：US6133097A
公开(公告)日：2000-10-17
申请号：US133969
申请日：1998-08-14
申请人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。栅电极中心的图案源极线槽向下堆叠到衬底。在源线插槽的底部形成源区。在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。形成自对准漏极区。

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