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1. 发明申请

US20130016133A1 BACKLIGHT MODULE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME 审中-公开
标题翻译：背光模组和液晶显示装置
公开(公告)号：US20130016133A1
公开(公告)日：2013-01-17
申请号：US13467991
申请日：2012-05-09
申请人： Chia-Hsin Chen , Tsung-Ping Wei , Chiu-Yuan Lin
发明人： Chia-Hsin Chen , Tsung-Ping Wei , Chiu-Yuan Lin
IPC分类号： G09G3/36 , G09G5/10 , F21V13/04 , G02F1/13357 , F21V8/00 , F21V13/02
CPC分类号： G09G3/3426 , G02B6/0031 , G02B6/0073 , G02B6/0075 , G02B6/0083 , G09G3/3413 , G09G2320/0238
摘要： A backlight module and a liquid crystal display (LCD) device using the same are provided. The backlight module includes a light-guide plate and a light source module. The light-guide plate has a first side surface and a second side surface, wherein the second side surface is tangent with the first side surface. The light source module is disposed beside the first side surface and the second side surface of the light-guide plate, and a plurality of first light emitting diode (LED) units and a plurality of second LED units are respectively disposed at portions of the light source module that face the first side surface and the second side surface of the light-guide plate. Thereby, the backlight module has the advantages of high image contrast and low power consumption offered by a direct type backlight module and maintains the thickness of a side-edge backlight module.
摘要翻译：提供了使用其的背光模块和液晶显示（LCD）装置。背光模块包括导光板和光源模块。导光板具有第一侧表面和第二侧表面，其中第二侧表面与第一侧表面相切。光源模块设置在导光板的第一侧表面和第二侧表面旁边，并且多个第一发光二极管（LED）单元和多个第二LED单元分别设置在光的部分源模块，其面对导光板的第一侧面和第二侧面。因此，背光模块具有由直接型背光模块提供的高图像对比度和低功耗的优点，并且保持侧边背光模块的厚度。

2. 发明申请

US20070146170A1 VIDEO PROCESSING METHOD AND APPARATUS 有权
标题翻译：视频处理方法和设备
公开(公告)号：US20070146170A1
公开(公告)日：2007-06-28
申请号：US11424612
申请日：2006-06-16
申请人： Chia-Hsin Chen , Chiu-Yuan Lin , Bor-Yuh Chang
发明人： Chia-Hsin Chen , Chiu-Yuan Lin , Bor-Yuh Chang
IPC分类号： H03M7/00
CPC分类号： H04N5/14
摘要： A video processing method and apparatus to employing an analog user interface and a digital video decoder. A working mode is provided, according to which analog control signals from the analog user interface are selectively directed to an analog-to-digital converter. The analog control signal is converted to digital control signal to accordingly control the digital video decoder.
摘要翻译：一种采用模拟用户界面和数字视频解码器的视频处理方法和装置。提供工作模式，根据该工作模式，来自模拟用户界面的模拟控制信号被选择性地引导到模数转换器。模拟控制信号被转换为数字控制信号，从而相应地控制数字视频解码器。

3. 发明授权

US07358882B2 Video processing method and apparatus 有权
标题翻译：视频处理方法和装置
公开(公告)号：US07358882B2
公开(公告)日：2008-04-15
申请号：US11424612
申请日：2006-06-16
申请人： Chia-Hsin Chen , Chiu-Yuan Lin , Bor-Yuh Chang
发明人： Chia-Hsin Chen , Chiu-Yuan Lin , Bor-Yuh Chang
IPC分类号： H03M1/66
CPC分类号： H04N5/14
摘要： A video processing method and apparatus to employing an analog user interface and a digital video decoder. A working mode is provided, according to which analog control signals from the analog user interface are selectively directed to an analog-to-digital converter. The analog control signal is converted to digital control signal to accordingly control the digital video decoder.
摘要翻译：一种采用模拟用户界面和数字视频解码器的视频处理方法和装置。提供工作模式，根据该工作模式，来自模拟用户界面的模拟控制信号被选择性地引导到模数转换器。模拟控制信号被转换为数字控制信号，从而相应地控制数字视频解码器。

4. 发明申请

US20070192517A1 APPARATUS FOR UPDATING AUDIOVISUAL EQUIPMENT AND METHOD THEREOF 审中-公开
标题翻译：更新音像设备的方法及其方法
公开(公告)号：US20070192517A1
公开(公告)日：2007-08-16
申请号：US11308890
申请日：2006-05-23
申请人： Bor-Yuh Chang , Chiu-Yuan Lin , Chia-Hsin Chen
发明人： Bor-Yuh Chang , Chiu-Yuan Lin , Chia-Hsin Chen
IPC分类号： G06F13/38
CPC分类号： H04N21/4586 , G06F8/65 , H04N21/41422 , H04N21/818
摘要： An Audiovisual equipment comprises a data input interface, an analog-to-digital (AD) converter, a retrieving circuit and a processing unit burnt with program codes is provided. The data input interface receives analog data from a data source carrying updating data therein. The A/D converter converts the analog data into digital data which is then transmitted to the retrieving circuit. The retrieving circuit retrieves updating data and then transfers it to the processing unit. The processing unit updates the program codes using the updating data.
摘要翻译：视听设备包括数据输入接口，模数（AD）转换器，检索电路和用程序代码烧毁的处理单元。数据输入接口从其中承载更新数据的数据源接收模拟数据。 A / D转换器将模拟数据转换成数字数据，然后发送到检索电路。检索电路检索更新数据，然后将其传送到处理单元。处理单元使用更新数据更新程序代码。

5. 发明申请

US20090172264A1 SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS 审中-公开
标题翻译：集成数据访问命令的系统和方法
公开(公告)号：US20090172264A1
公开(公告)日：2009-07-02
申请号：US12238152
申请日：2008-09-25
申请人： Chien-Ping Chung , Chia-Hsin Chen , Ming-Che Liu
发明人： Chien-Ping Chung , Chia-Hsin Chen , Ming-Che Liu
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0679 , G06F12/0246
摘要： A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory.
摘要翻译：数据访问命令集成方法包括以下步骤。首先，通过总线顺序地接收M个数据访问命令，其中包含在M个数据访问命令中的N个数据访问命令具有相同的命令类型并且遵循顺序地址关系。接下来，根据寻址序列重新排序N个数据访问命令，从而在数据存储器中顺序地访问对应于重新排序的N个数据访问命令的第一数据。

6. 发明授权

US06446172B1 Method and system for controlling the memory access operation performed by a central processing unit in a computer system 有权
标题翻译：用于控制由计算机系统中的中央处理单元执行的存储器访问操作的方法和系统
公开(公告)号：US06446172B1
公开(公告)日：2002-09-03
申请号：US09335602
申请日：1999-06-18
申请人： Chia-Hsin Chen , Nai-Shung Chang
发明人： Chia-Hsin Chen , Nai-Shung Chang
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F13/161
摘要： A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner than the prior art. This memory access control method and system is characterized by, for each read request from the CPU, the prompt transfer of the corresponding internal read-request signal to the memory control unit, right after it is issued and without waiting until the CPU issues the L1 write-back signal of the current read request. If the current read request is a hit to the cache memory, a read-stop signal is promptly issued to stop the current read operation on the memory unit, and then a cache write-back operation is performed to write the cache data back into the memory unit. This method and system can help reduce the period of waiting states by the CPU, thus increasing the overall memory access performance by the CPU and the overall system performance of the computer system.
摘要翻译：提供存储器访问控制方法和系统，用于在计算机系统上以比现有技术更有效的方式将中央处理单元（CPU）的存储器访问操作控制到存储器单元。这种存储器访问控制方法和系统的特征在于，对于来自CPU的每个读取请求，在相应的内部读取请求信号被发出之后立即将其传送到存储器控制单元，并且不等待直到CPU发出L1 当前读取请求的回写信号。如果当前读取请求是对高速缓存存储器的命中，则立即发出读停止信号以停止对存储器单元的当前读取操作，然后执行高速缓存回写操作以将高速缓存数据写回到存储单元该方法和系统可以帮助减少CPU等待状态的时间，从而提高CPU的整体内存访问性能以及计算机系统的整体系统性能。

7. 发明授权

US06278641B1 Method and apparatus capable of programmably delaying clock of DRAM 有权
标题翻译：能够可编程地延迟DRAM的时钟的方法和装置
公开(公告)号：US06278641B1
公开(公告)日：2001-08-21
申请号：US09578234
申请日：2000-05-24
申请人： Chia-Hsin Chen , Jiin Lai
发明人： Chia-Hsin Chen , Jiin Lai
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： An apparatus and method capable of programmably delaying a clock of a memory. The apparatus and method utilize the BIOS, external electric switches or other logic devices to selectively delay the clock of the DRAM and/or the internal clock of the north bridge, by which the DRAM has enough setup time at the rising edge of work clock to correctly read out the command word. The north bridge can then correctly receive data from the DRAM module and transfer the data to the CPU or AGP. Therefore, the memory can function normally even if the memory is operated at high speed or with heavy loading.
摘要翻译：一种能够可编程地延迟存储器的时钟的装置和方法。该装置和方法利用BIOS，外部电气开关或其他逻辑装置来选择性地延迟DRAM的时钟和/或北桥的内部时钟，由此DRAM在工作时钟的上升沿具有足够的建立时间正确读出命令字。然后，北桥可以从DRAM模块正确接收数据，并将数据传输到CPU或AGP。因此，即使存储器以高速或大负载运行，存储器也能正常工作。

8. 发明授权

US09104546B2 Method for performing block management using dynamic threshold, and associated memory device and controller thereof 有权
标题翻译：使用动态阈值执行块管理的方法，以及相关联的存储器件及其控制器
公开(公告)号：US09104546B2
公开(公告)日：2015-08-11
申请号：US13014735
申请日：2011-01-27
申请人： Chi-Lung Wang , Chia-Hsin Chen , Chien-Cheng Lin
发明人： Chi-Lung Wang , Chia-Hsin Chen , Chien-Cheng Lin
IPC分类号： G06F13/12 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/10 , G06F2212/7201
摘要： A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method.
摘要翻译：提供了一种执行块管理的方法。该方法应用于闪速存储器的控制器，其中闪速存储器包括多个块。该方法包括：根据至少一个条件调整动态阈值; 以及将所述多个块中的特定块的有效/无效页面计数与所述动态阈值进行比较，以确定是否擦除所述特定块。还提供了一种相关联的存储器件及其控制器，其中存储器件包括闪存和控制器。特别地，控制器包括被布置为存储程序代码的只读存储器（ROM），并且还包括微处理器，其被布置为执行程序代码以控制对闪存的访问并管理多个块，其中在微处理器，控制器根据方法进行操作。

9. 发明授权

US08195870B2 Memory card and method for handling data updating of a flash memory 有权
标题翻译：用于处理闪存的数据更新的存储卡和方法
公开(公告)号：US08195870B2
公开(公告)日：2012-06-05
申请号：US12050205
申请日：2008-03-18
申请人： Chia-Hsin Chen
发明人： Chia-Hsin Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.
摘要翻译：本发明提供了一种处理闪速存储器的数据更新的方法。在一个实施例中，闪速存储器包括母块，其包括要更新的多个更新的页面。首先，将不记录数据的备用块作为与母块对应的文件分配表（FAT）块而弹出。然后将用于更新母块的更新页面的数据写入FAT块的多个替换页面。最后，替换页面和更新页面之间的多个映射关系被记录在存储在FAT块中的页面映射表中。

10. 发明申请

US20090248965A1 HYBRID FLASH MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 审中-公开
标题翻译：混合闪速存储器装置及其控制方法
公开(公告)号：US20090248965A1
公开(公告)日：2009-10-01
申请号：US12401466
申请日：2009-03-10
申请人： Yuan-Huei Lee , Chi Chang , Chia-Hsin Chen , Ming-Che Liu
发明人： Yuan-Huei Lee , Chi Chang , Chia-Hsin Chen , Ming-Che Liu
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7202 , G06F2212/7208
摘要： A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size.
摘要翻译：提供一种混合式闪速存储装置和混合式闪速存储装置的控制方法。混合式闪速存储装置包括连接到主机总线的微控制器，用于经由主机总线从主机接收要写入混合式闪速存储器装置的数据; 以及耦合到所述微控制器的存储器模块。闪存模块包括第一类型的闪存和第二类闪存。当数据大小不大于预定数据大小时，数据被确定为被写入第一类闪速存储器的第一对数块中。相反，当数据大小大于预定数据大小时，确定数据被写入第二类闪存的第二对数块中。

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