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    • 1. 发明申请
    • I2C/SPI CONTROL INTERFACE CIRCUITRY, INTEGRATED CIRCUIT STRUCTURE, AND BUS STRUCTURE THEREOF
    • I2C / SPI控制接口电路,集成电路结构及总线结构
    • US20110161545A1
    • 2011-06-30
    • US12776473
    • 2010-05-10
    • Chi-Tung ChangHsiu Ming FanChuan-Ching Tsai
    • Chi-Tung ChangHsiu Ming FanChuan-Ching Tsai
    • G06F13/40
    • G06F13/4068G06F13/4022G06F2213/0016
    • An I2C/SPI control interface circuitry, an integrated circuit structure, and a bus structure thereof are provided. The I2C/SPI control interface circuitry includes an I2C control module and a SPI control module. The I2C control module has an I2C clock port and an I2C data port, and the SPI control module has a SPI clock port, a SPI data input port, a SPI data output port, and a SPI chip enable port. The I2C clock port is electrically connected with the SPI chip enable port to become an I2C clock/SPI chip enable input/output end. The I2C data port is electrically connected with the SPI data input port and the SPI data output port to become an I2C/SPI data input/output end. The SPI clock port is the SPI clock output end. The I2C and SPI control module are alternative to be enabled to avoid signal interference and lower the cost of the package and the manufacture of the integrated circuit.
    • 提供了I2C / SPI控制接口电路,集成电路结构及其总线结构。 I2C / SPI控制接口电路包括I2C控制模块和SPI控制模块。 I2C控制模块具有I2C时钟端口和I2C数据端口,SPI控制模块具有SPI时钟端口,SPI数据输入端口,SPI数据输出端口和SPI芯片使能端口。 I2C时钟端口与SPI芯片使能端口电连接,成为I2C时钟/ SPI芯片使能输入/输出端。 I2C数据端口与SPI数据输入端口和SPI数据输出端口电连接,成为I2C / SPI数据输入/输出端。 SPI时钟端口是SPI时钟输出端。 I2C和SPI控制模块是可以避免信号干扰的替代方案,降低了封装的成本和集成电路的制造。
    • 3. 发明授权
    • Flash memory storage device and read/write method
    • 闪存存储设备和读/写方式
    • US07516296B2
    • 2009-04-07
    • US11581430
    • 2006-10-17
    • Chi-Tung ChangChia-Wei HouKuo-Hsiang HsuWen-Hao Cheng
    • Chi-Tung ChangChia-Wei HouKuo-Hsiang HsuWen-Hao Cheng
    • G06F12/06
    • G06F12/0246
    • A memory storage device and a read/write method thereof, first defining logically the flash memory as at least one particular data management area and at least one common data management area; next, determining the logical block address located in the particular data management area or the common data management area according to data transmitted to an external system by an area decision mechanism, wherein the method of writing to the particular data management area is by using a method of dynamic deviation value, and the method of writing to the common data management area is by using a method of same displacement value. Whereby, the particular data management area can be avoided moving frequently caused by updating data from the external system to improve read/write performance of the flash memory.
    • 一种存储器存储设备及其读/写方法,首先将闪速存储器逻辑地定义为至少一个特定数据管理区域和至少一个公共数据管理区域; 接下来,根据通过区域判定机构发送给外部系统的数据来确定位于特定数据管理区域或公共数据管理区域中的逻辑块地址,其中写入特定数据管理区域的方法是使用方法 的动态偏差值,并且写入公共数据管理区域的方法是通过使用相同位移值的方法。 由此,可以避免特定的数据管理区域通过从外部系统更新数据而频繁地移动,以提高闪速存储器的读/写性能。
    • 4. 发明申请
    • Method to Access Storage Device Through Universal Serial Bus
    • 通过通用串行总线访问存储设备的方法
    • US20080276037A1
    • 2008-11-06
    • US12172672
    • 2008-07-14
    • Chi-Tung ChangChing-Wen Wang
    • Chi-Tung ChangChing-Wen Wang
    • G06F12/02
    • G06F3/0656G06F3/0613G06F3/0679
    • A method accessing a flash memory storage device through universal serial bus (USB) of the present invention includes a flash controller and a flash memory, wherein the method includes connecting the storage device to a USB interface of an electronic device; outputting a plurality of accessing instructions to the flash controller via the electronic device; deciding which data is needed to be temporarily saved in a cache memory and a priority of the accessing instructions according to the characteristic of the file system and the content of preceding instructions of the flash controller; and writing the data temporarily saved in the cache memory into the flash memory according to the priority of the flash controller. The objective of the method of the present invention is to enhance the operation efficiency of the storage device.
    • 通过本发明的通用串行总线(USB)访问闪存存储设备的方法包括闪存控制器和闪速存储器,其中该方法包括将存储设备连接到电子设备的USB接口; 经由电子设备向闪存控制器输出多个访问指令; 根据文件系统的特性和闪存控制器的前述指令的内容,确定需要临时保存在高速缓冲存储器中的数据和访问指令的优先级; 并根据闪存控制器的优先级将临时保存在高速缓冲存储器中的数据写入闪速存储器。 本发明的方法的目的是提高存储装置的操作效率。
    • 6. 发明申请
    • Integrated hub control chip
    • 集成集线器控制芯片
    • US20080120454A1
    • 2008-05-22
    • US11638481
    • 2006-12-14
    • Chi-Tung ChangShih-Min LanI-Chieh Lin
    • Chi-Tung ChangShih-Min LanI-Chieh Lin
    • G06F3/00
    • G06F13/4022G06F2213/0042
    • An integrated hub control chip is applied to a motherboard of an application system. The integrated hub control chip contains an upstream port transceiver, an upstream port controller, a relaying circuit unit, a keyboard control module, a digital camera control module, a storage medium control module, and a relaying circuit controller. The keyboard control module, the digital camera control module, and the storage medium control module are directly connected to the relaying circuit controller. The relaying circuit controller switches the transmission path of the relaying circuit unit according to the transmission speed of these control modules. The upstream port controller controls the transmission direction of the upstream port transceiver to accomplish the data communication with the motherboard. The objects of saving the circuit space of motherboard, reducing the hardware cost, and increasing the purposes and expansibility of the integrated hub control chip can therefore be achieved.
    • 将集成的集线器控制芯片应用于应用系统的主板。 集成集线器控制芯片包括上行端口收发器,上游端口控制器,中继电路单元,键盘控制模块,数字照相机控制模块,存储介质控制模块和中继电路控制器。 键盘控制模块,数码相机控制模块和存储介质控制模块直接连接到继电电路控制器。 中继电路控制器根据这些控制模块的传输速度切换中继电路单元的传输路径。 上行端口控制器控制上行端口收发器的传输方向,完成与主板的数据通信。 因此可以实现节省主板电路空间,降低硬件成本,增加集成集线器控制芯片的目的和可扩展性的目的。
    • 7. 发明申请
    • Design of a signal switch
    • 信号开关设计
    • US20070067553A1
    • 2007-03-22
    • US11216649
    • 2005-09-01
    • Chi-Tung Chang
    • Chi-Tung Chang
    • G06F13/00
    • G06F13/4072
    • The present invention provides an improved design of the signal switch, wherein the signal switch comprises at least one combinational logic such as a chip, a plurality of hosts and at least one set of input control device such as a keyboard and a mouse. The chip can further comprise one or more virtual keyboard controller and a plurality of hubs and a multiplexer. The multiplexer of the present invention is utilized to detect and interpret signals. The present invention utilizes the combinational logic design of the chips and the multiplexer to provide a signal switch that can share multi-upstream devices but less downstream ports, only one set of keyboard and mouse is required. Multiplexing downstream devices among multiple hubs, which are dedicated to upstream hosts, help reducing the whole enumeration process of time. The signal switch of the present invention provides an improved design by replacing the central processing units (CPU) of a conventional design of signal switch with the combinational logics such as chips in order to increase the speed of the enumeration, as a result, the enumerating time is thus reduced.
    • 本发明提供了信号开关的改进设计,其中信号开关包括至少一个组合逻辑,例如芯片,多个主机以及至少一组诸如键盘和鼠标之类的输入控制装置。 芯片还可以包括一个或多个虚拟键盘控制器和多个集线器以及多路复用器。 本发明的复用器用于检测和解释信号。 本发明利用芯片和复用器的组合逻辑设计来提供可以共享多上游设备但较少下游端口的信号交换机,仅需要一组键盘和鼠标。 专用于上游主机的多个集线器之间的多路复用下游设备有助于减少整个计时过程。 本发明的信号开关通过用诸如芯片的组合逻辑代替信号开关的常​​规设计的中央处理单元(CPU)来提供改进的设计,以便增加枚举的速度,结果是枚举 因此减少了时间。
    • 8. 发明申请
    • Portable data storage device
    • 便携式数据存储设备
    • US20050114570A1
    • 2005-05-26
    • US10720853
    • 2003-11-21
    • Chi-Tung ChangHung-Chou Tsai
    • Chi-Tung ChangHung-Chou Tsai
    • G06F13/12G06K19/077
    • G06K19/077G06K19/07732
    • A portable data storage device mainly includes a universal serial bus (USB) connector; a volatile memory for reading, writing, and storing data; a control chip connected between the USB connector and the volatile memory for serving as a transmission interface with an external electronic apparatus; a charging battery for providing power needed by the volatile memory to store data; and a battery charging circuit connected between the USB connector and the charging battery for charging the charging battery, so that the portable data storage device has increased data processing speed and may be produced at lowered cost.
    • 便携式数据存储装置主要包括通用串行总线(USB)连接器; 用于读取,写入和存储数据的易失性存储器; 连接在USB连接器和易失性存储器之间的控制芯片,用作与外部电子设备的传输接口; 用于提供易失性存储器所需的电力以存储数据的充电电池; 以及连接在USB连接器和充电电池之间用于对充电电池充电的电池充电电路,使得便携式数据存储装置具有增加的数据处理速度并且可以以降低的成本生产。
    • 10. 发明申请
    • COMPUTER PERIPHERAL APPARATUS
    • 电脑外围设备
    • US20110202692A1
    • 2011-08-18
    • US12758821
    • 2010-04-13
    • Chi-Tung ChangI-Chieh Lin
    • Chi-Tung ChangI-Chieh Lin
    • G06F3/00
    • G06F1/1632G06F2213/0038
    • The present invention discloses a computer peripheral apparatus. The computer peripheral apparatus includes an USB hub, at least one build-in card reader, and a controller. Each build-in card reader is electrically connected to one built-in downstream port of the USB hub. The controller connects to the USB hub and the build-in card reader to monitor the connection requirement of the build-in card reader. When the controller determines the build-in card reader does not need to be kept connected, the controller sets the status of its corresponding built-in downstream port as a “first status,” which defines the corresponding built-in downstream port is not connected. Thus, the computer system is informed that the built-in downstream port is not connected. Therefore, if there are no USB devices connecting to other downstream ports of the USB hub, the entire computer peripheral apparatus can enter into hibernation mode, thereby lowering the power consumption
    • 本发明公开了一种计算机外围设备。 计算机外围设备包括USB集线器,至少一个内置读卡器和控制器。 每个内置读卡器电连接到USB集线器的一个内置下游端口。 控制器连接到USB集线器和内置读卡器,以监控内置读卡器的连接要求。 当控制器确定内置读卡器不需要保持连接时,控制器将其对应的内置下行端口的状态设置为“第一状态”,定义相应的内置下行端口未连接 。 因此,通知计算机系统内置下游端口未连接。 因此,如果没有USB设备连接到USB集线器的其他下游端口,则整个计算机外围设备可以进入休眠模式,从而降低功耗