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1. 发明授权

US08650511B2 Lithography performance check methods and apparatus 有权
标题翻译：光刻性能检查方法和仪器
公开(公告)号：US08650511B2
公开(公告)日：2014-02-11
申请号：US12770903
申请日：2010-04-30
申请人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
发明人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.
摘要翻译：本公开提供了许多不同的实施例。提供了一种掩模制造方法和系统。该方法和系统确定已经经历光学邻近校正的集成电路（IC）设计布局的关键区域。关键领域是受控IC设计布局的热点地区。然后对OPCed IC设计布局的关键区域进行光刻工艺检查。

2. 发明申请

US20110271239A1 Lithography Performance Check Methods and Apparatus 有权
标题翻译：光刻性能检测方法与仪器
公开(公告)号：US20110271239A1
公开(公告)日：2011-11-03
申请号：US12770903
申请日：2010-04-30
申请人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
发明人： Chi-Ta Lu , Peng-Ren Chen , Dong-Hsu Cheng , Chang-Jyh Hsieh
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.
摘要翻译：本公开提供了许多不同的实施例。提供了一种掩模制造方法和系统。该方法和系统确定已经经历光学邻近校正的集成电路（IC）设计布局的关键区域。关键领域是受控IC设计布局的热点地区。然后对OPCed IC设计布局的关键区域进行光刻工艺检查。

3. 发明申请

US20130268901A1 Structure and Method for E-Beam Writing 有权
标题翻译：电子束写作的结构与方法
公开(公告)号：US20130268901A1
公开(公告)日：2013-10-10
申请号：US13442635
申请日：2012-04-09
申请人： Chi-Ta Lu , Jia-Guei Jou , Yi-Hsien Chen , Peng-Ren Chen , Dong-Hsu Cheng
发明人： Chi-Ta Lu , Jia-Guei Jou , Yi-Hsien Chen , Peng-Ren Chen , Dong-Hsu Cheng
IPC分类号： G06F17/50
CPC分类号： H01J37/3174 , G03F1/36 , G03F1/70 , G03F7/70441 , G06F17/5081 , G06F2217/12 , H01J37/3026 , H01J2237/31764
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.
摘要翻译：本公开提供了集成电路（IC）方法的一个实施例。该方法包括接收具有主要特征的IC设计布局; 对设计布局执行光学邻近校正（OPC）过程; 然后对设计布局进行点动减速处理，使得设计布局的点动特征减少。

4. 发明授权

US09136092B2 Structure and method for E-beam writing 有权
标题翻译：电子束写入的结构和方法
公开(公告)号：US09136092B2
公开(公告)日：2015-09-15
申请号：US13442635
申请日：2012-04-09
申请人： Chi-Ta Lu , Jia-Guei Jou , Yi-Hsien Chen , Peng-Ren Chen , Dong-Hsu Cheng
发明人： Chi-Ta Lu , Jia-Guei Jou , Yi-Hsien Chen , Peng-Ren Chen , Dong-Hsu Cheng
IPC分类号： G06F17/50 , G03F1/00 , H01J37/317 , G03F1/36 , G03F1/70 , H01J37/302 , G03F7/20
CPC分类号： H01J37/3174 , G03F1/36 , G03F1/70 , G03F7/70441 , G06F17/5081 , G06F2217/12 , H01J37/3026 , H01J2237/31764
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.
摘要翻译：本公开提供了集成电路（IC）方法的一个实施例。该方法包括接收具有主要特征的IC设计布局; 对设计布局执行光学邻近校正（OPC）过程; 然后对设计布局进行点动减速处理，使得设计布局的点动特征减少。

5. 发明授权

US08458631B2 Cycle time reduction in data preparation 有权
标题翻译：数据准备中的周期时间缩短
公开(公告)号：US08458631B2
公开(公告)日：2013-06-04
申请号：US13207691
申请日：2011-08-11
申请人： Chi-Ta Lu , Jia-Guei Jou , Peng-Ren Chen , Dong-Hsu Cheng
发明人： Chi-Ta Lu , Jia-Guei Jou , Peng-Ren Chen , Dong-Hsu Cheng
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70441 , G06F17/5081
摘要： The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.
摘要翻译：本公开提供了减少数据准备中的周期时间的方法。在一个实施例中，一种方法包括接收初始集成电路（IC）设计布局和光学邻近校正（OPC）处理的初始IC设计布局，以及接收修订的IC设计布局。该方法还包括将修订的IC设计布局与初始IC设计布局进行比较，以从初始IC设计布局识别修订的IC设计布局的差异区域，在修订的IC设计布局的差异区域上执行OPC，并且合并 OPC处理差分区域的修订后的IC设计布局与OPC处理的初始IC设计布局。

6. 发明申请

US20130042210A1 CYCLE TIME REDUCTION IN DATA PREPARATION 有权
标题翻译：数据准备中的循环时间减少
公开(公告)号：US20130042210A1
公开(公告)日：2013-02-14
申请号：US13207691
申请日：2011-08-11
申请人： Chi-Ta Lu , Jia-Guei Jou , Peng-Ren Chen , Dong-Hsu Cheng
发明人： Chi-Ta Lu , Jia-Guei Jou , Peng-Ren Chen , Dong-Hsu Cheng
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70441 , G06F17/5081
摘要： The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.
摘要翻译：本公开提供了减少数据准备中的周期时间的方法。在一个实施例中，一种方法包括接收初始集成电路（IC）设计布局和光学邻近校正（OPC）处理的初始IC设计布局，以及接收修订的IC设计布局。该方法还包括将修订的IC设计布局与初始IC设计布局进行比较，以从初始IC设计布局识别修订的IC设计布局的差异区域，在修订的IC设计布局的差异区域上执行OPC，并且合并 OPC处理差分区域的修订后的IC设计布局与OPC处理的初始IC设计布局。

7. 发明授权

US08555211B2 Mask making with error recognition 有权
标题翻译：面具制作与错误识别
公开(公告)号：US08555211B2
公开(公告)日：2013-10-08
申请号：US13416897
申请日：2012-03-09
申请人： Jia-Guei Jou , Kuan-Chi Chen , Peng-Ren Chen , Dong-Hsu Cheng
发明人： Jia-Guei Jou , Kuan-Chi Chen , Peng-Ren Chen , Dong-Hsu Cheng
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F1/36
摘要： A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.
摘要翻译：制作掩模的方法包括从设计者接收IC设计布局，应用逻辑操作（LOP）校正，执行OPC校正，将修改后的数据分解为电子束格式的多个主要特征，以及发送电子波束格式数据到掩模编写器用于掩模制造。在该方法中实施XOR操作，以检查和验证在OPC修改和/或数据断裂期间是否丢失模式。对于具有小于最大OPC校正的临界尺寸（CD）尺寸的多个主要特征的方法也实施了BACKBONE XOR操作，以检查和验证在OPC修改和/或数据断裂期间是否丢失小图案特征 45纳米以上的半导体技术。

8. 发明申请

US20130239072A1 MASK MAKING WITH ERROR RECOGNITION 有权
标题翻译：屏蔽错误识别
公开(公告)号：US20130239072A1
公开(公告)日：2013-09-12
申请号：US13416897
申请日：2012-03-09
申请人： Jia-Guei Jou , Kuan-Chi Chen , Peng-Ren Chen , Dong-Hsu Cheng
发明人： Jia-Guei Jou , Kuan-Chi Chen , Peng-Ren Chen , Dong-Hsu Cheng
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F1/36
摘要： A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.
摘要翻译：制作掩模的方法包括从设计者接收IC设计布局，应用逻辑操作（LOP）校正，执行OPC校正，将修改后的数据分解为电子束格式的多个主要特征，以及发送电子波束格式数据到掩模编写器用于掩模制造。在该方法中实施XOR操作，以检查和验证在OPC修改和/或数据断裂期间是否丢失模式。对于具有小于最大OPC校正的临界尺寸（CD）尺寸的多个主要特征的方法也实施了BACKBONE XOR操作，以检查和验证在OPC修改和/或数据断裂期间是否丢失小图案特征 45纳米以上的半导体技术。

9. 发明申请

US20080263501A1 System, Method, and Computer-Readable Medium for Performing Data Preparation for a Mask Design 有权
标题翻译：用于进行掩模设计数据准备的系统，方法和计算机可读介质
公开(公告)号：US20080263501A1
公开(公告)日：2008-10-23
申请号：US11738844
申请日：2007-04-23
申请人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
发明人： Peng-Ren Chen , Chien-Chao Huang , Chih-Chiang Tu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed
摘要翻译：提供了一种用于执行数据准备的方法，计算机可读介质和系统。接收集成电路设计，并且调用多个预光学邻近校正处理，使得并行地执行多个预光学邻近校正处理。响应于多个预光学邻近校正处理中的每一个已经完成的确定来调用光学邻近校正处理。响应于光学邻近校正处理已经完成的确定，调用后光学邻近校正处理

10. 发明申请

US20110272719A1 LED STRUCTURE 有权
标题翻译： LED结构
公开(公告)号：US20110272719A1
公开(公告)日：2011-11-10
申请号：US12776834
申请日：2010-05-10
申请人： Peng-Ren Chen , Hsueh-Hsing Liu , Jen-Inn Chyi
发明人： Peng-Ren Chen , Hsueh-Hsing Liu , Jen-Inn Chyi
IPC分类号： H01L33/32
CPC分类号： H01L33/14 , H01L33/04
摘要： The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0≦x≦1, 0≦y≦1, and 0≦x+y≦1.
摘要翻译：本发明公开了一种LED结构，其中N型电流扩展层插入在N型半导体层之间以均匀地分布流过N型半导体层的电流。 N型电流扩展层包括从低带隙到较高带隙的顺序堆叠的至少三个子层，其中具有较低带隙的子层在衬底附近，并且子层具有较高带隙的发光层靠近发光层。 N型电流扩展层的每个子层由通式In x Al y Ga（1-x-y）N表示，其中0＆nlE; x＆nlE; 1,0＆amp; nlE; y＆nlE; 1和0＆nlE; x + y＆nlE;

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