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1. 发明授权

US08638250B2 Amplifier, fully-differential amplifier and delta-sigma modulator 有权
标题翻译：放大器，全差分放大器和Δ-Σ调制器
公开(公告)号：US08638250B2
公开(公告)日：2014-01-28
申请号：US13590491
申请日：2012-08-21
申请人： Chen-Yen Ho , Chi-Lun Lo , Hung-Chieh Tsai , Yu-Hsin Lin
发明人： Chen-Yen Ho , Chi-Lun Lo , Hung-Chieh Tsai , Yu-Hsin Lin
IPC分类号： H03M3/00
CPC分类号： H03F1/0205 , H03F3/265 , H03F3/30 , H03F3/3023 , H03F3/45071 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/18 , H03F2203/30021 , H03F2203/30033 , H03F2203/45022 , H03F2203/45134 , H03F2203/45138 , H03M3/39 , H03M3/50
摘要： An amplifier, a fully-differential amplifier and a delta-sigma modulator are disclosed. The disclosed amplifier includes a front-end gain stage, an AC-coupled push-pull output stage and a compensation circuit. The compensation circuit is coupled between the front-end gain stage and an output terminal of the amplifier. The AC-coupled push-pull output stage uses an AC-coupled capacitor (which is a passive two terminal electrical component rather than a stray or parasitic capacitance of a transistor) to couple the front-end gain stage to a gate of a top or bottom transistor of a push-pull structure introduced in the AC-coupled push-pull output stage, and uses a resistance component to couple a gate of the top or bottom transistor (depending on which one is coupled to the AC-coupled capacitor) to a bias voltage level.
摘要翻译：公开了放大器，全差分放大器和Δ-Σ调制器。所公开的放大器包括前端增益级，AC耦合推挽输出级和补偿电路。补偿电路耦合在前端增益级与放大器的输出端之间。交流耦合推挽输出级使用交流耦合电容器（其是无源双端电气元件而不是晶体管的杂散或寄生电容），以将前端增益级耦合到顶部的栅极或引入到AC耦合推挽输出级中的推挽结构的底部晶体管，并且使用电阻分量将顶部或底部晶体管的栅极（取决于耦合到AC耦合电容器的栅极）耦合到偏置电压电平。

2. 发明授权

US07737775B2 Low-noise DC offset calibration circuit and related receiver stage 有权
标题翻译：低噪声直流偏移校准电路及相关接收器级
公开(公告)号：US07737775B2
公开(公告)日：2010-06-15
申请号：US12168159
申请日：2008-07-07
申请人： Chi-Lun Lo , Yu-Hsin Lin
发明人： Chi-Lun Lo , Yu-Hsin Lin
IPC分类号： H03F1/02
CPC分类号： H04B1/30 , H04L25/0296
摘要： A receiver stage has an operational amplifier, a feedback resistor coupled between an output of the operational amplifier and an input of the operational amplifier, and a DC offset calibration circuit. The DC offset calibration circuit includes a plurality of resistors and a plurality of switches. Each resistor has a first end coupled to a supply voltage. First ends of each of the switches are coupled to second ends of each of the resistors, respectively, and second ends of the switches are coupled to the input of the operational amplifier.
摘要翻译：接收机级具有运算放大器，耦合在运算放大器的输出端和运算放大器的输入端之间的反馈电阻器以及DC偏置校准电路。 DC偏移校准电路包括多个电阻器和多个开关。每个电阻器具有耦合到电源电压的第一端。每个开关的第一端分别耦合到每个电阻器的第二端，并且开关的第二端耦合到运算放大器的输入端。

3. 发明授权

US08890611B2 Operational amplifier circuits 有权
标题翻译：运算放大器电路
公开(公告)号：US08890611B2
公开(公告)日：2014-11-18
申请号：US13612784
申请日：2012-09-12
申请人： Hung-Chieh Tsai , Chi-Lun Lo , Chen-Yen Ho , Yu-Hsin Lin
发明人： Hung-Chieh Tsai , Chi-Lun Lo , Chen-Yen Ho , Yu-Hsin Lin
IPC分类号： H03F3/45 , H03F3/193 , H03F1/14 , H03F1/32 , H03F3/30
CPC分类号： H03F3/45179 , H03F1/14 , H03F1/3211 , H03F1/483 , H03F3/193 , H03F3/3023 , H03F3/45 , H03F3/45076 , H03F3/45188 , H03F2200/36 , H03F2203/45222 , H03F2203/45521 , H03F2203/45526 , H03F2203/45626
摘要： An operational amplifier circuit includes a first stage amplifier circuit, a second stage amplifier circuit and a first feedforward circuit. The first stage amplifier circuit is coupled to a first input node for receiving a first input signal and amplifying the first input signal to generate a first amplified signal. The second stage amplifier circuit is coupled to the first stage amplifier circuit for receiving the first amplified signal and amplifying the first amplified signal to generate a first output signal at a first output node. The first feedforward circuit is coupled between the first input node and the second stage amplifier circuit for feeding the first input signal forward to the second stage amplifier circuit.
摘要翻译：运算放大器电路包括第一级放大器电路，第二级放大器电路和第一前馈电路。第一级放大器电路耦合到第一输入节点，用于接收第一输入信号并放大第一输入信号以产生第一放大信号。第二级放大器电路耦合到第一级放大器电路，用于接收第一放大信号并放大第一放大信号以在第一输出节点产生第一输出信号。第一前馈电路耦合在第一输入节点和第二级放大器电路之间，用于将第一输入信号向前馈送到第二级放大器电路。

4. 发明申请

US20110181334A1 TRACK AND HOLD CIRCUIT AND RELATED RECEIVING DEVICE WITH TRACK AND HOLD CIRCUIT EMPLOYED THEREIN 有权
标题翻译：跟踪和保持电路跟踪和相关接收设备跟踪并保持已使用的电路
公开(公告)号：US20110181334A1
公开(公告)日：2011-07-28
申请号：US12695164
申请日：2010-01-28
申请人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
发明人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
IPC分类号： H03L5/00
CPC分类号： H03G3/3052 , H03G1/0088
摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
摘要翻译：运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。

5. 发明授权

US08575970B2 Track and hold circuit and related receiving device with track and hold circuit employed therein 有权
标题翻译：跟踪和保持电路及其中使用的跟踪和保持电路的相关接收设备
公开(公告)号：US08575970B2
公开(公告)日：2013-11-05
申请号：US12695164
申请日：2010-01-28
申请人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
发明人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
IPC分类号： H03K17/00
CPC分类号： H03G3/3052 , H03G1/0088
摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
摘要翻译：运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。

6. 发明授权

US07956680B2 Low-noise DC offset calibration circuit and related receiver stage 有权
标题翻译：低噪声直流偏移校准电路及相关接收器级
公开(公告)号：US07956680B2
公开(公告)日：2011-06-07
申请号：US12767812
申请日：2010-04-27
申请人： Chi-Lun Lo , Yu-Hsin Lin
发明人： Chi-Lun Lo , Yu-Hsin Lin
IPC分类号： H03F1/02
CPC分类号： H04B1/30
摘要： A DC offset calibration circuit has a first resistor, a first switch, a second resistor, and a second switch. The first resistor is coupled to a first supply voltage. The first switch is coupled to the first resistor, to a first input of an amplifier, and to a first input resistor. A second end of the first input resistor is not coupled to the first supply voltage. The second resistor is coupled to a second supply voltage. The second switch is coupled to the second resistor, to a second input of the amplifier, and to a first end of a second input resistor. A second end of the second input resistor is not coupled to the second supply voltage.
摘要翻译： DC偏移校准电路具有第一电阻器，第一开关，第二电阻器和第二开关。第一电阻器耦合到第一电源电压。第一开关耦合到第一电阻器，耦合到放大器的第一输入端和第一输入电阻器。第一输入电阻器的第二端不耦合到第一电源电压。第二电阻耦合到第二电源电压。第二开关耦合到第二电阻器，耦合到放大器的第二输入端和第二输入电阻器的第一端。第二输入电阻器的第二端不耦合到第二电源电压。

7. 发明申请

US20100201423A1 Low-noise DC Offset Calibration Circuit and Related Receiver Stage 有权
标题翻译：低噪声直流偏移校准电路和相关接收器级
公开(公告)号：US20100201423A1
公开(公告)日：2010-08-12
申请号：US12767812
申请日：2010-04-27
申请人： Chi-Lun Lo , Yu-Hsin Lin
发明人： Chi-Lun Lo , Yu-Hsin Lin
IPC分类号： H03L5/00
CPC分类号： H04B1/30
摘要： A DC offset calibration circuit has a first resistor, a first switch, a second resistor, and a second switch. The first resistor is coupled to a first supply voltage. The first switch is coupled to the first resistor, to a first input of an amplifier, and to a first input resistor. A second end of the first input resistor is not coupled to the first supply voltage. The second resistor is coupled to a second supply voltage. The second switch is coupled to the second resistor, to a second input of the amplifier, and to a first end of a second input resistor. A second end of the second input resistor is not coupled to the second supply voltage.
摘要翻译： DC偏移校准电路具有第一电阻器，第一开关，第二电阻器和第二开关。第一电阻器耦合到第一电源电压。第一开关耦合到第一电阻器，耦合到放大器的第一输入端和第一输入电阻器。第一输入电阻器的第二端不耦合到第一电源电压。第二电阻耦合到第二电源电压。第二开关耦合到第二电阻器，耦合到放大器的第二输入端和第二输入电阻器的第一端。第二输入电阻器的第二端不耦合到第二电源电压。

8. 发明申请

US20100001792A1 Low-noise DC Offset Calibration Circuit and Related Receiver Stage 有权
标题翻译：低噪声直流偏移校准电路和相关接收器级
公开(公告)号：US20100001792A1
公开(公告)日：2010-01-07
申请号：US12168159
申请日：2008-07-07
申请人： Chi-Lun Lo , Yu-Hsin Lin
发明人： Chi-Lun Lo , Yu-Hsin Lin
IPC分类号： H03F1/02
CPC分类号： H04B1/30 , H04L25/0296
摘要： A receiver stage has an operational amplifier, a feedback resistor coupled between an output of the operational amplifier and an input of the operational amplifier, and a DC offset calibration circuit. The DC offset calibration circuit includes a plurality of resistors and a plurality of switches. Each resistor has a first end coupled to a supply voltage. First ends of each of the switches are coupled to second ends of each of the resistors, respectively, and second ends of the switches are coupled to the input of the operational amplifier.
摘要翻译：接收机级具有运算放大器，耦合在运算放大器的输出端和运算放大器的输入端之间的反馈电阻器以及DC偏置校准电路。 DC偏移校准电路包括多个电阻器和多个开关。每个电阻器具有耦合到电源电压的第一端。每个开关的第一端分别耦合到每个电阻器的第二端，并且开关的第二端耦合到运算放大器的输入端。

9. 发明授权

US08891707B2 Receiving device and method thereof 有权
标题翻译：接收装置及其方法
公开(公告)号：US08891707B2
公开(公告)日：2014-11-18
申请号：US12761411
申请日：2010-04-16
申请人： Chi-Lun Lo , Chia-Hsin Wu , Tsung-Ling Li
发明人： Chi-Lun Lo , Chia-Hsin Wu , Tsung-Ling Li
IPC分类号： H04B1/10 , H04B1/30
CPC分类号： H04B1/30
摘要： A receiving device includes: a mixer module arranged to receive an input signal to generate a down-converted output; a first active filter, the first active filter arranged to receive the down-converted output and perform an active filtering process upon the down-converted output to generate a first filtered output; a passive filter, the passive filter arranged to receive the first filtered output and perform a passive filtering process upon the first filtered output to generate a second filtered output; and a processing circuit, the processing circuit arranged to receive the second filtered output and process the second filtered output to generate an output signal corresponding to the input signal.
摘要翻译：接收装置包括：混合器模块，被布置成接收输入信号以产生下变频输出; 第一有源滤波器，所述第一有源滤波器被布置为接收所述经下变频的输出，并且对所述经下变频的输出执行有源滤波处理以产生第一滤波输出; 无源滤波器，无源滤波器被布置为接收第一滤波输出并且在第一滤波输出上执行无源滤波处理以产生第二滤波输出; 以及处理电路，所述处理电路被布置为接收所述第二滤波输出并处理所述第二滤波输出以产生对应于所述输入信号的输出信号。

10. 发明申请

US20170033801A1 METHOD AND APPARATUS FOR EXCESS LOOP DELAY COMPENSATION IN DELTA-SIGMA MODULATOR 审中-公开
标题翻译：在DELTA-SIGMA调制器中进行循环延迟补偿的方法和装置
公开(公告)号：US20170033801A1
公开(公告)日：2017-02-02
申请号：US15112691
申请日：2015-01-20
申请人： Chi-Lun LO , Stacy HO , MediaTek Singapore Pte. Ltd.
发明人： Chi-Lun Lo , Stacy Ho
IPC分类号： H03M3/00
CPC分类号： H03M3/422 , H03M3/37 , H03M3/424 , H03M3/50
摘要： A delta-sigma modulator includes a signal subtraction circuit, a loop filter, a quantizer, a digital-to-analog converter (DAC), and a control circuit. The signal subtraction circuit subtracts an analog feedback signal from an analog input signal to generate a difference signal. The loop filter performs a filtering operation upon the difference signal to generate a filtered signal. The quantizer quantizes the filtered signal into a digital out put signal, wherein at least one inherent circuit characteristic of the quantizer are adjusted in response to a digital code input. The DAC generates the analog feedback signal according to the digital output signal. The control circuit generates the digital code input to the quantizer for setting an excess loop delay (ELD) compensation.
摘要翻译： Δ-Σ调制器包括信号减法电路，环路滤波器，量化器，数模转换器（DAC）和控制电路。信号减法电路从模拟输入信号中减去模拟反馈信号，生成差分信号。环路滤波器对差分信号执行滤波操作以产生滤波信号。量化器将经滤波的信号量化为数字输出信号，其中响应于数字代码输入调整量化器的至少一个固有电路特性。 DAC根据数字输出信号产生模拟反馈信号。控制电路产生输入到量化器的数字代码，用于设定多余的循环延迟（ELD）补偿。

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