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1. 发明授权

US6144100A Integrated circuit with bonding layer over active circuitry 失效
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US6144100A
公开(公告)日：2000-11-07
申请号：US959410
申请日：1997-10-28
申请人： Chi-Cheong Shen , Donald C. Abbott , Walter Bucksch , Marco Corsi , Taylor Rice Efland , John P. Erdeljac , Louis Nicholas Hutter , Quang Mai , Konrad Wagensohner , Charles Edward Williams
发明人： Chi-Cheong Shen , Donald C. Abbott , Walter Bucksch , Marco Corsi , Taylor Rice Efland , John P. Erdeljac , Louis Nicholas Hutter , Quang Mai , Konrad Wagensohner , Charles Edward Williams
IPC分类号： H01L23/485 , H01L23/48 , H01L23/52
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/45124 , H01L2224/45144 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48744 , H01L2224/48755 , H01L2224/48764 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3025
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A 2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

2. 发明授权

US06683380B2 Integrated circuit with bonding layer over active circuitry 有权
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US06683380B2
公开(公告)日：2004-01-27
申请号：US10191453
申请日：2002-07-10
申请人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
发明人： Taylor R. Efland , Donald C. Abbott , Walter Bucksch , Marco Corsi , Chi-Cheong Shen , John P. Erdeljac , Louis N. Hutter , Quang X. Mai , Konrad Wagensohner , Charles E. Williams , Milton L. Buschbom
IPC分类号： H01L2348
CPC分类号： H01L24/49 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05552 , H01L2224/05554 , H01L2224/05644 , H01L2224/05664 , H01L2224/0603 , H01L2224/1147 , H01L2224/13099 , H01L2224/131 , H01L2224/45124 , H01L2224/45144 , H01L2224/48463 , H01L2224/4847 , H01L2224/48644 , H01L2224/48664 , H01L2224/48764 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2224/4945 , H01L2224/85191 , H01L2924/0001 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48744
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A-2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

3. 发明授权

US5278461A Integrated transistor circuit 失效
标题翻译：集成晶体管电路
公开(公告)号：US5278461A
公开(公告)日：1994-01-11
申请号：US006579
申请日：1993-01-21
申请人： Walter Bucksch , Anton Vorel
发明人： Walter Bucksch , Anton Vorel
IPC分类号： H03F1/30 , G05F3/20
CPC分类号： H03F1/302
摘要： The invention relates to an integrated transistor circuit comprising a transistor (Q1) of which the collector is connected to an input of a circuit (S) and between the base and collector of which an antisaturation diode (D1) is connected. According to the invention a further current branch is provided between the base and the emitter and includes a series circuit of a diode (D2) and a resistor (R1). As a result, a leakage current flowing in reverse direction into the antisaturation diode (D1) flows via the diode (D2) and the resistor (R1) and not via the emitter-base path of the transistor (Q1) and consequently amplification of the leakage current is prevented.
摘要翻译：本发明涉及一种集成晶体管电路，其包括晶体管（Q1），其晶体管（Q1）与集电极连接到电路（S）的输入端，并且其基极和集电极之间连接有抗饱和二极管（D1）。根据本发明，在基极和发射极之间提供另外的电流分支，并且包括二极管（D2）和电阻器（R1）的串联电路。结果，反向流入抗饱和二极管（D1）的漏电流通过二极管（D2）和电阻器（R1）而不通过晶体管（Q1）的发射极 - 基极路径流动，防止漏电流。

4. 发明授权

US5952869A High power MOS transistor 失效
标题翻译：大功率MOS晶体管
公开(公告)号：US5952869A
公开(公告)日：1999-09-14
申请号：US686850
申请日：1996-07-26
申请人： Frank Fattori , Walter Bucksch , Erich Bayer , Kevin Scoones
发明人： Frank Fattori , Walter Bucksch , Erich Bayer , Kevin Scoones
IPC分类号： H01L27/088 , H01L21/8234 , H03F3/68 , H03K17/12 , H03K19/0175 , H03K17/62 , H03K17/693 , H03K17/76
CPC分类号： H03K17/122 , H01L2924/0002
摘要： A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).
摘要翻译：高功率MOS晶体管由大量并联连接的子晶体管（T1至T6）组成。子晶体管（T1至T6）的栅电极可以通过可控开关元件（SW1至SW6; SQ1至SQ5）单独驱动。

5. 发明授权

US5600176A Integrated voltage divider 失效
标题翻译：集成分压器
公开(公告)号：US5600176A
公开(公告)日：1997-02-04
申请号：US458547
申请日：1995-06-02
申请人： Walter Bucksch
发明人： Walter Bucksch
IPC分类号： H01C7/22 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/08 , H03H5/02 , H03H7/01 , H01L29/00 , H01L23/62
CPC分类号： H01L27/0688 , H01L27/0802
摘要： Integrated voltage divider comprising partial resistors (R1 ,R2) formed of paths of polycrystalline semiconductor material applied over a dielectric layer (4) on a semiconductor substrate (5). Under the paths, each forming a partial resistor (R1,R2) in the semiconductor substrate (5), a well (6 and 7 respectively) is formed having a conductivity type opposite to the conductivity type of the semiconductor substrate (5). The total surfaces of the paths forming the partial resistors (R1,R2) are dimensioned so that their ratio equals the inverse ratio of the resistor values of the two partial resistors (R1 ,R2).
摘要翻译：集成分压器包括由半导体衬底（5）上的介电层（4）上施加的多晶半导体材料的路径形成的部分电阻（R1，R2）。在半导体衬底（5）内形成一个部分电阻（R1，R2）的路径下，形成具有与半导体衬底（5）的导电类型相反的导电类型的阱（6和7）。形成部分电阻器（R1，R2）的路径的总表面的尺寸被确定为它们的比值等于两个部分电阻器（R1，R2）的电阻器值的反比。

6. 发明授权

US4686602A Protective circuit arrangement for protecting semiconductor components 失效
标题翻译：用于保护半导体元件的保护电路装置
公开(公告)号：US4686602A
公开(公告)日：1987-08-11
申请号：US737962
申请日：1985-05-28
申请人： Walter Bucksch
发明人： Walter Bucksch
IPC分类号： H02H9/04 , H01L21/822 , H01L23/62 , H01L27/02 , H01L27/04 , H01L27/06 , H02H7/20
CPC分类号： H01L27/0248
摘要： A protective circuit arrangement is described for protecting semiconductor components connected to input and output terminals (10) against overvoltages in bipolar integrated circuits. The circuit arrangement contains at least one supply voltage terminal (12) and a ground terminal (14). Between the ground terminal (14) and at least the input and output terminals (10) which are connected to components sensitive to overvoltage a thyristor-tetrode (22) having a first control electrode (28) and a second control electrode (30) is inserted, the first control electrode (28) being connected to a line (18) which in the operative state of the integrated circuit lies at a voltage above the ground potential and the second control electrode (30) being connected to the ground terminal 14.
摘要翻译：描述了用于保护连接到输入和输出端子（10）的半导体部件以防止双极集成电路中的过电压的保护电路装置。电路装置包括至少一个电源电压端子（12）和接地端子（14）。在与第一控制电极（28）和第二控制电极（30）的可控硅 - 四极（22）连接到对过电压敏感的部件的至少输入输出端子（10）之间的接地端子（14）插入时，第一控制电极（28）连接到在集成电路的工作状态下处于高于地电位的电压的线（18），而第二控制电极（30）连接到接地端子14。

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