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1. 发明授权

US6144100A Integrated circuit with bonding layer over active circuitry 失效
标题翻译：在有源电路上具有接合层的集成电路
公开(公告)号：US6144100A
公开(公告)日：2000-11-07
申请号：US959410
申请日：1997-10-28
申请人： Chi-Cheong Shen , Donald C. Abbott , Walter Bucksch , Marco Corsi , Taylor Rice Efland , John P. Erdeljac , Louis Nicholas Hutter , Quang Mai , Konrad Wagensohner , Charles Edward Williams
发明人： Chi-Cheong Shen , Donald C. Abbott , Walter Bucksch , Marco Corsi , Taylor Rice Efland , John P. Erdeljac , Louis Nicholas Hutter , Quang Mai , Konrad Wagensohner , Charles Edward Williams
IPC分类号： H01L23/485 , H01L23/48 , H01L23/52
CPC分类号： H01L24/05 , H01L2224/04042 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/45124 , H01L2224/45144 , H01L2224/48644 , H01L2224/48655 , H01L2224/48664 , H01L2224/48744 , H01L2224/48755 , H01L2224/48764 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/3025
摘要： An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A 2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.
摘要翻译：一种具有直接在其有源电路上的接合表面（12）的集成电路器件（10），以及制造这种集成电路的方法（图2A 2E）。为了形成接合表面（12），晶片（20）在其金属化层（21）上设有通孔（24），然后涂覆有种子金属层（25）。电镀图案（26）形成在晶片（20）上，暴露种子金属层（25）的部分并阻挡种子金属层（25）的其余部分。这些暴露部分镀有连续的金属层（27,28,29），由此形成具有填充通孔（24）的多个层叠堆叠（200）的接合表面（12）。然后除去种子金属层（25）的电镀图案和非电镀部分。

2. 发明申请

US20110151634A1 LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC 有权
标题翻译：排水延伸电磁场的横向排水扩散型MOSFET
公开(公告)号：US20110151634A1
公开(公告)日：2011-06-23
申请号：US13027734
申请日：2011-02-15
申请人： Marie Denison , Taylor Rice Efland
发明人： Marie Denison , Taylor Rice Efland
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66704
摘要： An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall. A source region (18) of the first doping type is in the body region (16), a drain region (20) of the first doping type is in the drift region (14), and interconnects (521) are operable to electrically connect the one or more transistors to each other on the integrated circuit (200).
摘要翻译：集成电路（200）包括在具有半导体表面层的衬底（10）上或衬底（10）中的多个晶体管（210）中的一个，所述表面层具有顶表面。至少一个晶体管是漏极延伸的金属氧化物半导体（DEMOS）晶体管（210）。 DEMOS晶体管包括在表面层中具有第一掺杂剂类型的漂移区域（14），表面层的一部分中或之上的场电介质（23），以及在该层内的第二掺杂剂类型（16）的体区漂移区（14）。身体区域（16）具有从表面层的顶表面沿相邻场介电区域的电介质壁的至少一部分向下延伸的主体壁。门电介质（21）位于体壁的至少一部分上。导电栅电极（22）位于体壁上的栅电介质（21）上。第一掺杂型的源极区域（18）位于体区（16）中，第一掺杂型漏区（20）位于漂移区（14）中，互连（521）可操作以电连接集成电路（200）上的一个或多个晶体管彼此相连。

3. 发明申请

US20110108914A1 MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
公开(公告)号：US20110108914A1
公开(公告)日：2011-05-12
申请号：US13006566
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/78
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

4. 发明授权

US08253193B2 MOS transistor with gate trench adjacent to drain extension field insulation 有权
公开(公告)号：US08253193B2
公开(公告)日：2012-08-28
申请号：US13006566
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/66
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

5. 发明授权

US08173510B2 Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric 有权
标题翻译：横向漏极扩展MOSFET具有沿漏极延伸电介质侧壁的沟道
公开(公告)号：US08173510B2
公开(公告)日：2012-05-08
申请号：US13027734
申请日：2011-02-15
申请人： Marie Denison , Taylor Rice Efland
发明人： Marie Denison , Taylor Rice Efland
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66704
摘要： An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of the surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall. A source region (18) of the first doping type is in the body region (16), a drain region (20) of the first doping type is in the drift region (14), and interconnects (521) are operable to electrically connect the one or more transistors to each other on the integrated circuit (200).
摘要翻译：集成电路（200）包括在具有半导体表面层的衬底（10）上或衬底（10）中的多个晶体管（210）中的一个，所述表面层具有顶表面。至少一个晶体管是漏极延伸的金属氧化物半导体（DEMOS）晶体管（210）。 DEMOS晶体管包括在表面层中具有第一掺杂剂类型的漂移区域（14），表面层的一部分中或之上的场电介质（23），以及在该层内的第二掺杂剂类型（16）的体区漂移区（14）。身体区域（16）具有从表面层的顶表面沿相邻场介电区域的电介质壁的至少一部分向下延伸的主体壁。门电介质（21）位于体壁的至少一部分上。导电栅电极（22）位于体壁上的栅电介质（21）上。第一掺杂型的源极区域（18）位于体区（16）中，第一掺杂型漏区（20）位于漂移区（14）中，互连（521）可操作以电连接集成电路（200）上的一个或多个晶体管彼此相连。

6. 发明授权

US07888732B2 Lateral drain-extended MOSFET having channel along sidewall of drain extension dielectric 有权
标题翻译：横向漏极扩展MOSFET具有沿漏极延伸电介质侧壁的沟道
公开(公告)号：US07888732B2
公开(公告)日：2011-02-15
申请号：US12101762
申请日：2008-04-11
申请人： Marie Denison , Taylor Rice Efland
发明人： Marie Denison , Taylor Rice Efland
IPC分类号： H01L29/66
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66704
摘要： An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall. A source region (18) of the first doping type is in the body region (16), a drain region (20) of the first doping type is in the drift region (14), and interconnects (521) are operable to electrically connect the one or more transistors to each other on the integrated circuit (200).
摘要翻译：集成电路（200）包括在具有半导体表面层的衬底（10）上或衬底（10）中的多个晶体管（210）中的一个，所述表面层具有顶表面。至少一个晶体管是漏极延伸的金属氧化物半导体（DEMOS）晶体管（210）。 DEMOS晶体管包括在表面层中具有第一掺杂剂类型的移动区域（14），位于所述表面层的一部分中或之上的场电介质（23），以及在所述表面层内的第二掺杂剂类型（16）的体区漂移区（14）。身体区域（16）具有从表面层的顶表面沿相邻场介电区域的电介质壁的至少一部分向下延伸的主体壁。门电介质（21）位于体壁的至少一部分上。导电栅电极（22）位于体壁上的栅电介质（21）上。第一掺杂型的源极区域（18）位于体区（16）中，第一掺杂型漏区（20）位于漂移区（14）中，互连（521）可操作以电连接集成电路（200）上的一个或多个晶体管彼此相连。

7. 发明申请

US20090256212A1 LATERAL DRAIN-EXTENDED MOSFET HAVING CHANNEL ALONG SIDEWALL OF DRAIN EXTENSION DIELECTRIC 有权
标题翻译：排水延伸电磁场的横向排水扩散型MOSFET
公开(公告)号：US20090256212A1
公开(公告)日：2009-10-15
申请号：US12101762
申请日：2008-04-11
申请人： Marie Denison , Taylor Rice Efland
发明人： Marie Denison , Taylor Rice Efland
IPC分类号： H01L29/00 , H01L21/8236
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66704
摘要： An integrated circuit (200) includes one of more transistors (210) on or in a substrate (10) having semiconductor surface layer, the surface layer having a top surface. At least one of the transistors are drain extended metal-oxide-semiconductor (DEMOS) transistor (210). The DEMOS transistor includes a drift region (14) in the surface layer having a first dopant type, a field dielectric (23) in or on a portion of said surface layer, and a body region of a second dopant type (16) within the drift region (14). The body region (16) has a body wall extending from the top surface of the surface layer downwards along at least a portion of a dielectric wall of an adjacent field dielectric region. A gate dielectric (21) is on at least a portion of the body wall. An electrically conductive gate electrode (22) is on the gate dielectric (21) on the body wall. A source region (18) of the first doping type is in the body region (16), a drain region (20) of the first doping type is in the drift region (14), and interconnects (521) are operable to electrically connect the one or more transistors to each other on the integrated circuit (200).
摘要翻译：集成电路（200）包括在具有半导体表面层的衬底（10）上或衬底（10）中的多个晶体管（210）中的一个，所述表面层具有顶表面。至少一个晶体管是漏极延伸的金属氧化物半导体（DEMOS）晶体管（210）。 DEMOS晶体管包括在表面层中具有第一掺杂剂类型的移动区域（14），位于所述表面层的一部分中或之上的场电介质（23），以及在所述表面层内的第二掺杂剂类型（16）的体区漂移区（14）。身体区域（16）具有从表面层的顶表面沿相邻场介电区域的电介质壁的至少一部分向下延伸的主体壁。门电介质（21）位于体壁的至少一部分上。导电栅电极（22）位于体壁上的栅电介质（21）上。第一掺杂型的源极区域（18）位于体区（16）中，第一掺杂型漏区（20）位于漂移区（14）中，互连（521）可操作以电连接集成电路（200）上的一个或多个晶体管彼此相连。

8. 发明申请

US20110111569A1 MOS TRANSISTOR WITH GATE TRENCH ADJACENT TO DRAIN EXTENSION FIELD INSULATION 有权
标题翻译：具有栅极扩展的MOS晶体管与漏极扩展场绝缘相邻
公开(公告)号：US20110111569A1
公开(公告)日：2011-05-12
申请号：US13006589
申请日：2011-01-14
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

9. 发明授权

US07893499B2 MOS transistor with gate trench adjacent to drain extension field insulation 有权
标题翻译： MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻
公开(公告)号：US07893499B2
公开(公告)日：2011-02-22
申请号：US12417810
申请日：2009-04-03
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/66
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

10. 发明申请

US20100252882A1 MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation 有权
标题翻译： MOS晶体管，栅极沟槽与漏极延伸场绝缘相邻
公开(公告)号：US20100252882A1
公开(公告)日：2010-10-07
申请号：US12417810
申请日：2009-04-03
申请人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
发明人： Marie Denison , Sameer Pendharkar , Binghua Hu , Taylor Rice Efland , Sridhar Seetharaman
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7825 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66689 , H01L29/66704
摘要： An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.
摘要翻译：一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的沟槽栅极。体阱和源极扩散区域与栅极沟槽的底表面重叠。一种包含MOS晶体管的集成电路，其具有与漂移区上的隔离电介质层邻接的第一沟槽栅极和位于重掺杂掩埋层上方的第二沟槽栅极。埋层是与漂移区相同的导电类型。形成包含MOS晶体管的集成电路的过程，其包括在晶体管的漏极的漂移区上方的隔离电介质层和形成在栅极沟槽中的栅极，该栅极与隔离电介质层相邻。通过去除与隔离电介质层相邻的衬底材料形成栅极沟槽。

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