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1. 发明授权

US07190604B2 Capacity dividable memory IC 有权
标题翻译：容量分配存储器IC
公开(公告)号：US07190604B2
公开(公告)日：2007-03-13
申请号：US11166586
申请日：2005-06-27
申请人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
发明人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
IPC分类号： G11C5/06 , G11C8/00 , G11C11/06
CPC分类号： G11C5/06
摘要： Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.
摘要翻译：晶片上的两个存储区域通过传输晶体管耦合以使每个区域的存储器容量加倍，并且可以锯切以产生两个具有单个存储器区域的存储器芯片。当传输晶体管导通时，一对传输晶体管用于将两个存储区域中的每个专用功能焊盘耦合。传输晶体管对之间的连接可以被锯切以产生单容量存储器芯片。通过将更多的存储区域与传输晶体管连接可以进一步增加存储器容量。

2. 发明申请

US20060285419A1 Flexible capacity memory IC 审中-公开
标题翻译：灵活容量存储IC
公开(公告)号：US20060285419A1
公开(公告)日：2006-12-21
申请号：US11153264
申请日：2005-06-16
申请人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
发明人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C2207/105
摘要： More than one memory areas are connected in parallel to increase the memory capacity when activated. The different memory area in a single unit die is activated by a selector pad which controls a single-pole, double throw switch to enable or disable the different memory areas. The corresponding pads of like memory areas are interconnected.
摘要翻译：并行连接多个存储器区域以增加激活时的存储容量。单个单元管芯中的不同存储区域由控制单极双掷开关的选择器板激活，以启用或禁用不同的存储区域。类似存储区域的相应焊盘是相互连接的。

3. 发明申请

US20060291264A1 Capacity dividable memory IC 有权
标题翻译：容量分配存储器IC
公开(公告)号：US20060291264A1
公开(公告)日：2006-12-28
申请号：US11166586
申请日：2005-06-27
申请人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
发明人： Chi-Cheng Hung , Ling-Yueh Chang , Pwu-Yueh Chung
IPC分类号： G11C5/06
CPC分类号： G11C5/06
摘要： Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.
摘要翻译：晶片上的两个存储区域通过传输晶体管耦合以使每个区域的存储器容量加倍，并且可以锯切以产生两个具有单个存储器区域的存储器芯片。当传输晶体管导通时，一对传输晶体管用于将两个存储区域中的每个专用功能焊盘耦合。传输晶体管对之间的连接可以被锯切以产生单容量存储器芯片。通过将更多的存储区域与传输晶体管连接可以进一步增加存储器容量。

4. 发明授权

US07245028B2 Split control pad for multiple signal 有权
标题翻译：分离控制板用于多个信号
公开(公告)号：US07245028B2
公开(公告)日：2007-07-17
申请号：US11141792
申请日：2005-06-02
申请人： Chi-Cheng Hung , Ling-Yueh Chang
发明人： Chi-Cheng Hung , Ling-Yueh Chang
IPC分类号： H01L23/48
CPC分类号： H01L24/02 , H01L23/50 , H01L2924/01005 , H01L2924/14 , H01L2924/19043
摘要： A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so that a default output is 1,0. When the split control pad is bonded with outside Vdd or Vss, both sections output “1,1” or “0,0” respectively. One of three possible logic word combinations can be selected to use for an IC.
摘要翻译：控制板被分成两部分，用于输出从集成电路中由00,01和11组成的组中选择的三个信号之一。每个部分内部连接到不同的电压源，例如表示逻辑“1”的Vdd，或表示逻辑“0”的Vss，默认输出为1,0。当分离控制板与Vdd或Vss外部接合时，两个部分分别输出“1,1”或“0,0”。可以选择三种可能的逻辑字组合中的一种用于IC。

5. 发明申请

US20070018271A1 Split control pad for multiple signal 有权
公开(公告)号：US20070018271A1
公开(公告)日：2007-01-25
申请号：US11141792
申请日：2005-06-02
申请人： Chi-Cheng Hung , Ling-Yueh Chang
发明人： Chi-Cheng Hung , Ling-Yueh Chang
IPC分类号： H01L31/00
CPC分类号： H01L24/02 , H01L23/50 , H01L2924/01005 , H01L2924/14 , H01L2924/19043
摘要： A control pad is split into two sections for output one of three signals selected from the group consisted of 00, 01, and 11 on an integrated circuit. Each section is internally connected to different voltage sources, say Vdd which represents logical “1”, or Vss which represents logical “0”, so that a default output is 1,0. When the split control pad is bonded with outside Vdd or Vss, both sections output “1,1” or “0,0” respectively. One of three possible logic word combinations can be selected to use for an IC.

6. 发明授权

US08759928B2 Image sensor cross-talk reduction system and method 有权
标题翻译：图像传感器串扰减少系统及方法
公开(公告)号：US08759928B2
公开(公告)日：2014-06-24
申请号：US13439628
申请日：2012-04-04
申请人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Chi-Cheng Hung , Jun-Nan Nian , Chih-Chung Chang
发明人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Chi-Cheng Hung , Jun-Nan Nian , Chih-Chung Chang
IPC分类号： H01L31/02 , H01L27/14
CPC分类号： H01L31/1804 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/1464 , H01L27/14683 , H01L31/103 , Y02E10/547
摘要： A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.
摘要翻译：提供了一种用于减少互补金属氧化物半导体背面照明图像传感器中的串扰的系统和方法。一个实施例包括在金属化层的基板的相对侧上的像素区域周围形成网格。栅格可以由诸如具有富含（110）的晶体取向的钨的材料形成。该方向有助于防止在格栅图案化过程中发生的缺陷。

7. 发明授权

US08572519B2 Method and apparatus for reducing implant topography reflection effect 有权
标题翻译：减少种植体形貌反射效应的方法和装置
公开(公告)号：US08572519B2
公开(公告)日：2013-10-29
申请号：US12758147
申请日：2010-04-12
申请人： Wen Hao Liu , Hsien-Huang Liao , Chi-Cheng Hung , Wen-Chun Huang , Ru-Gun Liu
发明人： Wen Hao Liu , Hsien-Huang Liao , Chi-Cheng Hung , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a corresponding developed photoresist feature of a photoresist layer; modifying the CD of the design feature to compensate for the difference, thereby generating a modified IC design layout; and making a mask using the modified IC design layout.
摘要翻译：本公开的实施例提供用于集成电路的方法和装置。一种示例性的集成电路（IC）方法包括提供包括设计特征的IC设计布局; 确定所述设计特征和光致抗蚀剂层的相应展开的光致抗蚀剂特征之间的尺寸差; 修改设计特征的CD以补偿差异，从而生成修改的IC设计布局; 并使用修改的IC设计布局制作面具。

8. 发明申请

US20110223753A1 Hard Mask Removal for Semiconductor Devices 有权
标题翻译：半导体器件的硬掩模去除
公开(公告)号：US20110223753A1
公开(公告)日：2011-09-15
申请号：US12724157
申请日：2010-03-15
申请人： Sheng-Hsiung Wang , Fu-Kai Yang , Yuan-Ching Peng , Chi-Cheng Hung
发明人： Sheng-Hsiung Wang , Fu-Kai Yang , Yuan-Ching Peng , Chi-Cheng Hung
IPC分类号： H01L21/3065 , H01L21/28
CPC分类号： H01L21/31144 , H01L21/28017 , H01L21/31116 , H01L29/66795
摘要： A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an embodiment, the structures are gate electrodes having a hard mask formed thereon and the spacers are spacers formed alongside the gate electrodes. A photoresist layer is formed over the protective layer, and the photoresist layer may be patterned to remove a portion of the photoresist layer over portions of the protective layer. Thereafter, an etch-back process is performed, such that the protective layer adjacent to the spacers remains to substantially protect the spacers. The hard mask is then removed while the protective layer protects the spacers.
摘要翻译：提供了在制造半导体器件期间去除硬掩模的方法。在衬底上形成的结构上形成诸如底部抗反射涂层（BARC）层或其它电介质层的保护层，其中间隔物沿着结构形成。在一个实施例中，结构是具有形成在其上的硬掩模的栅电极，并且间隔物是与栅电极一起形成的间隔物。在保护层上形成光致抗蚀剂层，并且可以对光致抗蚀剂层进行图案化以在保护层的部分上去除光致抗蚀剂层的一部分。此后，执行回蚀处理，使得与间隔物相邻的保护层保持基本上保护间隔物。然后去除硬掩模，同时保护层保护间隔物。

9. 发明授权

US5710573A Scaled video output overlaid onto a computer graphics output 失效
标题翻译：缩放的视频输出覆盖在计算机图形输出上
公开(公告)号：US5710573A
公开(公告)日：1998-01-20
申请号：US434974
申请日：1995-05-04
申请人： Chi-Cheng Hung , Jack Chang , Rong-Fuh Shyu , Wen-I Chu
发明人： Chi-Cheng Hung , Jack Chang , Rong-Fuh Shyu , Wen-I Chu
IPC分类号： H04N5/262 , G06T3/40 , G09G5/00 , G09G5/14 , G09G5/36 , G09G5/377 , G09G5/391 , G09G5/395 , H04N5/265 , H04N9/75 , G06F15/66
CPC分类号： H04N5/265 , G06T3/40 , G09G5/391 , G09G5/395 , H04N9/75 , G09G2340/125
摘要： A display control apparatus is provided to generate a scaled video output overlaid onto a computer graphics output. The display control apparatus includes a timing generator, adapted to receive a horizontal synchronization signal of the computer graphics output and the pixel number of horizontal scan line of the scaled video output, for generating a pixel clock of scaled video output and a horizontal lock signal; a scaling buffer, storing a video digital pixel data and having an output port generating the scaled video output, responsive to the pixel clock of scaled video output; an overlay controller, coupled to a controller bus and receiving an analog pixel data of the computer graphics output and, responsive to the pixel clock of scaled video output, the horizontal lock signal and a vertical synchronization signal of the computer graphics output, for overlaying the scaled video output onto the computer graphics output.
摘要翻译：提供显示控制装置以产生叠加在计算机图形输出上的缩放视频输出。显示控制装置包括定时发生器，用于接收计算机图形输出的水平同步信号和缩放视频输出的水平扫描线的像素数，用于产生缩放视频输出的像素时钟和水平锁定信号; 缩放缓冲器，存储视频数字像素数据，并具有产生缩放视频输出的输出端口，响应缩放视频输出的像素时钟; 覆盖控制器，耦合到控制器总线并接收计算机图形输出的模拟像素数据，并且响应于缩放视频输出的像素时钟，水平锁定信号和计算机图形输出的垂直同步信号，以覆盖缩放视频输出到计算机图形输出。

10. 发明申请

US20130264668A1 Image Sensor Cross-Talk Reduction System and Method 有权
标题翻译：图像传感器串扰减少系统和方法
公开(公告)号：US20130264668A1
公开(公告)日：2013-10-10
申请号：US13439628
申请日：2012-04-04
申请人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Chi-Cheng Hung , Jun-Nan Nian , Chih-Chung Chang
发明人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Chi-Cheng Hung , Jun-Nan Nian , Chih-Chung Chang
IPC分类号： H01L31/02
CPC分类号： H01L31/1804 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/1464 , H01L27/14683 , H01L31/103 , Y02E10/547
摘要： A system and method for reducing cross-talk in complementary metal oxide semiconductor back side illuminated image sensors is provided. An embodiment comprises forming a grid around the pixel regions on an opposite side of the substrate than metallization layers. The grid may be formed of a material such as tungsten with a (110)-rich crystalline orientation. This orientation helps prevents defects that can occur during patterning of the grid.
摘要翻译：提供了一种用于减少互补金属氧化物半导体背面照明图像传感器中的串扰的系统和方法。一个实施例包括在金属化层的基板的相对侧上的像素区域周围形成网格。栅格可以由诸如具有富含（110）的晶体取向的钨的材料形成。该方向有助于防止在格栅图案化过程中发生的缺陷。

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