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1. 发明授权

US07701262B2 Transmission line drivers and serial interface data transmission devices including the same 有权
标题翻译：传输线驱动器和串行接口数据传输设备包括相同
公开(公告)号：US07701262B2
公开(公告)日：2010-04-20
申请号：US11880492
申请日：2007-07-23
申请人： Chi Won Kim , Ji Young Kim , Myoung Bo Kwak , Jong Shin Shin , Seung Hee Yang , Hyun-Goo Kim , Jae Hyun Park
发明人： Chi Won Kim , Ji Young Kim , Myoung Bo Kwak , Jong Shin Shin , Seung Hee Yang , Hyun-Goo Kim , Jae Hyun Park
IPC分类号： H03B1/00
CPC分类号： H03K19/0016 , H03K19/018528 , H04L25/0276 , H04L25/028
摘要： A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.
摘要翻译：提供一种传输线驱动器和包括其的串行接口数据传输装置。传输线驱动器包括：预驱动器，被配置为基于串行传输数据信号产生和输出差分输入数据信号;差分放大器，被配置为接收差分输入数据信号并输出差分输出数据信号;以及共模控制器被配置为在空闲模式下将差分输出数据信号驱动到预定的共模电压。因此，可以降低功耗并且可以支持共模规范。

2. 发明授权

US09094023B2 Fractional-N phase locked loop, operation method thereof, and devices having the same 有权
标题翻译：分数N锁相环，其操作方法和具有该锁相环的装置
公开(公告)号：US09094023B2
公开(公告)日：2015-07-28
申请号：US13228520
申请日：2011-09-09
申请人： Jong Shin Shin
发明人： Jong Shin Shin
IPC分类号： H03D3/24 , H03L7/081 , H03L7/18 , H03L7/099 , H03L7/197 , H04L27/00
CPC分类号： H03L7/081 , H03L7/0996 , H03L7/18 , H03L7/1974 , H04L27/0014 , H04L2027/0053 , H04L2027/0069
摘要： A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.
摘要翻译：提供了一个分数N锁相环。分数N锁相环包括相位调整电路，其检测参考时钟信号和反馈时钟信号之间的相位差，并响应于检测到的相位差输出多个相位时钟信号，相位选择器选择并输出响应于相位选择信号从相位调整电路输出的多个相位时钟信号，控制电路，通过使用Σ-Δ调制器操作时钟信号产生相位选择信号，该Σ-Δ调制器操作时钟信号是通过将选择的相位时钟信号除以每个N个或更多个不同的整数（N是大于或等于2的整数），以及通过将所选择的相位时钟信号除以整数来产生反馈时钟信号的第一分频器。

3. 发明申请

US20120063521A1 FRACTIONAL-N PHASE LOCKED LOOP, OPERATION METHOD THEREOF, AND DEVICES HAVING THE SAME 有权
标题翻译：分段N相锁定环路，其操作方法及其相关设备
公开(公告)号：US20120063521A1
公开(公告)日：2012-03-15
申请号：US13228520
申请日：2011-09-09
申请人： Jong Shin Shin
发明人： Jong Shin Shin
IPC分类号： H03D3/24 , H03L7/08 , H04L27/00
CPC分类号： H03L7/081 , H03L7/0996 , H03L7/18 , H03L7/1974 , H04L27/0014 , H04L2027/0053 , H04L2027/0069
摘要： A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.
摘要翻译：提供了一个分数N锁相环。分数N锁相环包括相位调整电路，其检测参考时钟信号和反馈时钟信号之间的相位差，并响应于检测到的相位差输出多个相位时钟信号，相位选择器选择并输出响应于相位选择信号从相位调整电路输出的多个相位时钟信号，控制电路，通过使用Σ-Δ调制器操作时钟信号产生相位选择信号，该Σ-Δ调制器操作时钟信号是通过将选择的相位时钟信号除以每个N个或更多个不同的整数（N是大于或等于2的整数），以及通过将所选择的相位时钟信号除以整数来产生反馈时钟信号的第一分频器。

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