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    • 1. 发明授权
    • Fractional-N phase locked loop, operation method thereof, and devices having the same
    • 分数N锁相环,其操作方法和具有该锁相环的装置
    • US09094023B2
    • 2015-07-28
    • US13228520
    • 2011-09-09
    • Jong Shin Shin
    • Jong Shin Shin
    • H03D3/24H03L7/081H03L7/18H03L7/099H03L7/197H04L27/00
    • H03L7/081H03L7/0996H03L7/18H03L7/1974H04L27/0014H04L2027/0053H04L2027/0069
    • A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.
    • 提供了一个分数N锁相环。 分数N锁相环包括相位调整电路,其检测参考时钟信号和反馈时钟信号之间的相位差,并响应于检测到的相位差输出多个相位时钟信号,相位选择器选择并输出 响应于相位选择信号从相位调整电路输出的多个相位时钟信号,控制电路,通过使用Σ-Δ调制器操作时钟信号产生相位选择信号,该Σ-Δ调制器操作时钟信号是通过将选择的相位时钟信号除以 每个N个或更多个不同的整数(N是大于或等于2的整数),以及通过将所选择的相位时钟信号除以整数来产生反馈时钟信号的第一分频器。
    • 2. 发明申请
    • FRACTIONAL-N PHASE LOCKED LOOP, OPERATION METHOD THEREOF, AND DEVICES HAVING THE SAME
    • 分段N相锁定环路,其操作方法及其相关设备
    • US20120063521A1
    • 2012-03-15
    • US13228520
    • 2011-09-09
    • Jong Shin Shin
    • Jong Shin Shin
    • H03D3/24H03L7/08H04L27/00
    • H03L7/081H03L7/0996H03L7/18H03L7/1974H04L27/0014H04L2027/0053H04L2027/0069
    • A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.
    • 提供了一个分数N锁相环。 分数N锁相环包括相位调整电路,其检测参考时钟信号和反馈时钟信号之间的相位差,并响应于检测到的相位差输出多个相位时钟信号,相位选择器选择并输出 响应于相位选择信号从相位调整电路输出的多个相位时钟信号,控制电路,通过使用Σ-Δ调制器操作时钟信号产生相位选择信号,该Σ-Δ调制器操作时钟信号是通过将选择的相位时钟信号除以 每个N个或更多个不同的整数(N是大于或等于2的整数),以及通过将所选择的相位时钟信号除以整数来产生反馈时钟信号的第一分频器。