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1. 发明授权

US08559235B2 Nonvolatile memory device, operating method thereof and memory system including the same 有权
公开(公告)号：US08559235B2
公开(公告)日：2013-10-15
申请号：US13045661
申请日：2011-03-11
申请人： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
发明人： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
IPC分类号： G11C11/34
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/06 , G11C16/16 , H01L29/792
摘要： A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

2. 发明申请

US20120051143A1 NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件，其操作方法和包括其的存储器系统
公开(公告)号：US20120051143A1
公开(公告)日：2012-03-01
申请号：US13045661
申请日：2011-03-11
申请人： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
发明人： Chi Weon Yoon , Donghyuk Chae , Jae-Woo Park , Sang-Wan Nam
IPC分类号： G11C16/06
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/06 , G11C16/16 , H01L29/792
摘要： A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
摘要翻译：操作非易失性存储器件的方法包括对与多个串选择线（SSL）相关联的存储器单元执行擦除操作，与构成存储块的多个SSL相关联的存储器单元，以及将擦除操作在对与第一SSL相关联的第一存储器单元进行擦除操作之后，与第二SSL相关联的第二存储器单元。

3. 发明授权

US09798659B2 Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays 有权
公开(公告)号：US09798659B2
公开(公告)日：2017-10-24
申请号：US14837857
申请日：2015-08-27
申请人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
发明人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
IPC分类号： G06F12/06 , G06F3/06 , G11C5/02 , G11C11/56 , G11C16/04 , G11C8/10
CPC分类号： G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

4. 发明授权

US09036425B2 Memory devices for reducing boosting charge leakage and systems including the same 有权
标题翻译：用于减少增加电荷泄漏的存储器件及包括其的系统
公开(公告)号：US09036425B2
公开(公告)日：2015-05-19
申请号：US13229107
申请日：2011-09-09
申请人： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
发明人： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
IPC分类号： G11C16/06 , G11C16/04 , G11C16/34
CPC分类号： G11C16/0483 , G11C16/3418
摘要： A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.
摘要翻译：三维（3D）非易失性存储器包括存储单元阵列和合并驱动器，其被配置为将相同电平的合并电压施加到存储单元阵列中的公共源线和体。

5. 发明申请

US20120047321A1 Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays 审中-公开
标题翻译：用于具有三维存储器单元阵列的非易失性存储器件的地址调度方法
公开(公告)号：US20120047321A1
公开(公告)日：2012-02-23
申请号：US13213806
申请日：2011-08-19
申请人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
发明人： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
摘要翻译：至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或自然数大于2。

6. 发明申请

US20120063235A1 Memory Devices For Reducing Boosting Charge Leakage And Systems Including The Same 有权
标题翻译：用于减少增压充电泄漏和包括其的系统的存储器件
公开(公告)号：US20120063235A1
公开(公告)日：2012-03-15
申请号：US13229107
申请日：2011-09-09
申请人： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
发明人： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/3418
摘要： A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.
摘要翻译：三维（3D）非易失性存储器包括存储单元阵列和合并驱动器，其被配置为将相同电平的合并电压施加到存储单元阵列中的公共源线和体。

7. 发明授权

US06400640B2 Method for memory addressing 失效
标题翻译：存储器寻址方法
公开(公告)号：US06400640B2
公开(公告)日：2002-06-04
申请号：US09738324
申请日：2000-12-18
申请人： Ramchan Woo , Chi Weon Yoon , Hoi Jun Yoo
发明人： Ramchan Woo , Chi Weon Yoon , Hoi Jun Yoo
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： A Row-After-Column memory addressing method. The memory addressing method changes the order of addressing so as to enhance the efficiency of memory addressing. The Row-After-Column memory addressing method of the present invention comprises the steps of activating a column path by generating the column address when the address is input for data access, and activating a row path by generating the row address according to the address. Therefore, pipeline stall arising from inputting the column address (/CAS) subsequent to input of the row address (/RAS) can be eliminated and the speed of memory access can be enhanced.
摘要翻译：行后存储器寻址方法。存储器寻址方法改变了寻址的顺序，以提高存储器寻址的效率。本发明的行后列存储器寻址方法包括以下步骤：当输入地址用于数据访问时通过产生列地址来激活列路径，并且通过根据地址生成行地址来激活行路径。因此，可以消除在输入行地址（/ RAS）之后输入列地址（/ CAS）引起的流水线停顿，并且可以提高存储器访问的速度。

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